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PDF COP87L88CLV-XE Data sheet ( Hoja de datos )

Número de pieza COP87L88CLV-XE
Descripción 8-Bit One-Time Programmable OTP Microcontroller
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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PRELIMINARY
September 1996
COP87L88CL COP87L84CL 8-Bit
One-Time Programmable (OTP) Microcontroller
General Description
The COP87L88CL COP87L84CL OTP microcontrollers are
members of the COP8TM feature family using an 8-bit core
architecture It is pin and software compatible to the mask
ROM COP888CL COP884CL product family
(Continued)
Y Packages
44 PLCC with 39 I O pins
40 DIP with 33 I O pins
28 DIP with 24 I O pins
28 SO with 24 I O pins (contact local sales office for
availability)
Key Features
Y Two 16-bit timers each with two
supporting
Processor independent PWM mode
External event counter mode
Input capture mode
16-bit
registers
Y 4 kbytes on-board EPROM with security feature
Y 128 bytes on-board RAM
CPU Instruction Set Features
Y 1 ms instruction cycle time
Y Ten multi-source vectored interrupts servicing
External interrupt
Idle timer T0
Two timers (each with 2 Interrupts)
MICROWIRE PLUS
Multi-Input Wake Up
Software trap
Additional Peripheral Features
Default VIS (default interrupt)
Y Versatile and easy to use instruction set
Y Idle timer
Y 8-bit Stack Pointer SP stack in RAM
Y Multi-Input Wake-Up (MIWU) with optional interrupts (8) Y Two 8-bit register indirect data memory pointers
Y WATCHDOGTM and clock monitor logic
(B and X)
Y MICROWIRE PLUSTM serial I O
I O Features
Fully Static CMOS
Y Two power saving modes HALT and IDLE
Y Memory mapped I O
Y Single supply operation 2 7V – 5 5V
Y Software selectable I O options (TRI-STATE output Y Temperature range b40 C to a85 C
push-pull output
put)
weak pull-up input
high impedanceDina-taSDheevete4lUo.pcmoment Support
Y Schmitt trigger inputs on ports G and L
Y Emulation device for the COP888CL COP884CL
Y Real time emulation and full program debug offered by
MetaLink Development System
Block Diagram
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TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRE PLUSTM WATCHDOGTM MICROWIRETM and COP8TM are trademarks of National Semiconductor Corporation
PC is a registered trademark of International Business Machines Corporation
iceMASTERTM is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation TL DD12524
RRD-B30M106 Printed in U S A
TL DD 12524 – 16
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AC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified
Parameter
Conditions
Min Typ Max Units
Instruction Cycle Time (tc)
Crystal or Resonator
R C Oscillator
1 DC ms
3 DC
Inputs
tSETUP
tHOLD
Output Propagation Delay
tPD1 tPD0
SO SK
All Others
MICROWIRETM Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
RL e 2 2k CL e 100 pF
4V s VCC s 6V
4V s VCC s 6V
200
60
20
56
1
1
1
1
ns
ms
07
1
ns
220
tc
Reset Pulse Width
1 ms
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TL DD 12524 – 4
FIGURE 2 MICROWIRE PLUS Timing
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COP87L88CLV-XE arduino
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Timers (Continued)
et4U.com
FIGURE 7 Timer in External Event Counter Mode
TL DD 12524 – 10
Mode 3 Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block Tx in the
input capture mode
In this mode the timer Tx is constantly running at the fixed
tc rate The two registers RxA and RxB act as capture
registers Each register acts in conjunction with a pin The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin
flow interrupt pending flag in the Input Capture mode) Con-
sequently the TxC0 control bit should be reset when enter-
ing the Input Capture mode The timer underflow interrupt is
enabled with the TxENA control flag When a TxA interrupt
occurs in the Input Capture mode the user must check both
whether a TxA input capture or a timer underflow (or both)
caused the interrupt
Figure 8 shows a block diagram of the timer in Input Capture
mode
The timer value gets copied over into the register when a
TIMER CONTROL FLAGS
trigger event occurs on its corresponding pin Control bits
The timers T1 and T2 have indentical control structures
TxC3 TxC2 and TxC1 allow the trigger events to be speci-
The control bits and their functions are summarized below
fied either as a positive or a negative edge The trigger con-
dition for each input pin can be specified independently
TxC0
Timer Start Stop control in Modes 1 and 2
(Processor Independent PWM and External
The trigger conditions can also be programmed to generate
Event Counter) where 1 e Start 0 e Stop
interrupts The
on the TxA and
oTcxcBurpriennscweilol fbethreessppeecctifivieedlytrlaigtgcheer dcoinnDtdoiattihotenaSheet4U.comTMimodeer
Underflow Interrupt
3 (Input Capture)
Pending
Flag
in
pending flags TxPNDA and TxPNDB The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled Setting the TxENA flag enables interrupts to be
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
generated when the selected trigger condition occurs on the
TxENA Timer Interrupt Enable Flag
TxA pin Similarly the flag TxENB controls the interrupts
TxENB Timer Interrupt Enable Flag
from the TxB pin
1 e Timer Interrupt Enabled
Underflows from the timer can also be programmed to gen-
0 e Timer Interrupt Disabled
erate interrupts Underflows are latched into the timer TxC0
TxC3 Timer mode control
pending flag (the TxC0 control bit serves as the timer under-
TxC2 Timer mode control
TxC1 Timer mode control
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FIGURE 8 Timer in Input Capture Mode
11
TL DD 12524 – 11
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