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PDF ASM2I99456 Data sheet ( Hoja de datos )
| Número de pieza | ASM2I99456 | |
| Descripción | 3.3V/2.5V LVCMOS Clock Fanout Buffer | |
| Fabricantes | PulseCore | |
| Logotipo |  |
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November 2006
rev 0.3
ASM2I99456
3.3V/2.5V LVCMOS Clock Fanout Buffer
Features
• Configurable 10 outputs LVCMOS Clock
distribution buffer
• Compatible to single, dual and mixed 3.3V/2.5V
Voltage supply
• Wide range output clock frequency up to
250MHz
• Designed for mid-range to high-performance
telecom, networking and computer applications
• Supports high-performance differential clocking
applications
• Max. output skew of 200pS
(150pS within one bank)
• Selectable output configurations per output bank
• Tristatable outputs
• 32 LQFP and TQFP Packages
• Ambient Operating temperature range of
-40 to 85°C
• Pin and Function compatible to MPC9456
Functional Description
The ASM2I99456 is a 2.5V and 3.3V compatible 1:10 clock
distribution buffer designed for low-Voltage mid-range to
high-performance telecom, networking and computing
applications. Both 3.3V, 2.5V and dual supply voltages are
supported for mixed-voltage applications. The ASM2I99456
offers 10 low-skew outputs and a differential LVPECL clock
input. The outputs are configurable and support 1:1 and 1:2
output to input frequency ratios. The ASM2I99456 is
specified for the extended temperature range of –40 to
85°C.
The ASM2I99456 is a full static design supporting clock
frequencies up to 250 MHz. The signals are generated and
retimed on-chip to ensure minimal skew between the three
output banks.
Each of the three output banks can be individually supplied
by 2.5V or 3.3V supporting mixed voltage applications. The
FSELx pins choose between division of the input reference
frequency by one or two. The frequency divider can be set
individually for each of the three output banks. The
ASM2I99456 can be reset and the outputs are disabled by
deasserting the MR/OE pin (logic high state). Asserting
MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs
provide LVCMOS compatible levels with the capability to
drive terminated 50Ω transmission lines. The clock input is
low voltage PECL compatible for differential clock
distribution support. Please consult the ASM2I99446
specification for a full CMOS compatible device. For series
terminated transmission lines, each of the ASM2I99456
outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a
7x7 mm2 32-lead LQFP and TQFP Packages.
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
1 page  
November 2006
ASM2I99456
rev 0.3
Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = -40 to +85°C)1
Symbol
fref
fMAX
Characteristics
Input Frequency
Maximum Output
Frequency
Min Typ Max Unit
0 2502 MHz
÷1 output 0
2502 MHz
÷2 output 0
125 MHz
Condition
FSELx=0
FSELx=1
VPP
VCMR3
tP, REF
tr, tf
tPLH
tPHL
tPLZ, HZ
tPZL, LZ
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
PCLK
PCLK
500
1.3
1.4
CCLK to any Q
CCLK to any Q
2.2
2.2
1000 mV
VCC-
0.8
V
nS
1.04 nS
2.8 4.45 nS
2.8 4.2 nS
10 nS
10 nS
LVPECL
LVPECL
0.8 to 2.0V
tsk(O)
tsk(PP)
tSK(P)
Output-to-output
Skew
Within one bank
Any output bank, same output
divider
Any output, Any output divider
Device-to-device Skew
Output pulse skew5
150 pS
200 pS
350 pS
2.25 nS
200 pS
DCQ Output Duty Cycle
÷1 output 47 50 53 % DCREF = 50%
÷2 output 45 50 55 % DCREF = 25%-75%
tr, tf Output Rise/Fall Time
0.1
1.0 nS
0.55 to 2.4V
Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT.
2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.
3 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (AC) specification.
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
5 Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, TA = -40 to +85°C)
Symbol
Characteristics
Min
Typ
Max Unit
Condition
VIH Input high voltage
1.7 VCC + 0.3 V LVCMOS
VIL Input low voltage
-0.3 0.7 V LVCMOS
VPP
VCMR1
VOH
Peak-to-peak Input voltage
Common Mode Range
Output High Voltage
PCLK
PCLK
250
1.1
1.8
VCC-0.7
mV LVPECL
V LVPECL
V IOH=-24 mA 2
VOL Output Low Voltage
0.6 V IOL= 15 mA
ZOUT Output impedance
17 - 202
Ω
IIN Input current3
±200
µA VIN=GND or VIN=VCC
ICCQ4 Maximum Quiescent Supply Current
2.0 mA All VCC Pins
Note:1 VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (DC) specification.
2 The ASM2I99456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
3 Input pull-up / pull-down resistors influence input current.
4 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
5 of 14
5 Page 
November 2006
rev 0.3
Package Information
32-lead LQFP
ASM2I99456
SECTION A-A
Symbol
A
A1
A2
D
D1
E
E1
L
L1
T
T1
b
b1
R0
e
a
Dimensions
Inches
Millimeters
Min Max Min Max
….
0.0630
…
1.6
0.0020
0.0059
0.05
0.15
0.0531
0.0571
1.35
1.45
0.3465
0.3622
8.8
9.2
0.2717
0.2795
6.9
7.1
0.3465
0.3622
8.8
9.2
0.2717
0.2795
6.9
7.1
0.0177
0.0295
0.45
0.75
0.03937 REF
1.00 REF
0.0035
0.0079
0.09
0.2
0.0038
0.0062
0.097
0.157
0.0118
0.0177
0.30
0.45
0.0118
0.0157
0.30
0.40
0.0031
0.0079
0.08
0.20
0.031 BASE
0.8 BASE
0° 7° 0° 7°
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ASM2I99456.PDF ] | |
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