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H9DP32A4JJBCGR-KEM の電気的特性と機能

H9DP32A4JJBCGR-KEMのメーカーはHynixです、この部品の機能は「4GB eNAND Flash(x8) + 4Gb Mobile DDR (x32)」です。


製品の詳細 ( Datasheet PDF )

部品番号 H9DP32A4JJBCGR-KEM
部品説明 4GB eNAND Flash(x8) + 4Gb Mobile DDR (x32)
メーカ Hynix
ロゴ Hynix ロゴ 




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H9DP32A4JJBCGR-KEM Datasheet, H9DP32A4JJBCGR-KEM PDF,ピン配置, 機能
CI-MCP Specification
4GB eNAND Flash(x8)
+ 4Gb Mobile DDR (x32)
This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 0.1 / Nov. 2012
1

1 Page





H9DP32A4JJBCGR-KEM pdf, ピン配列
Preliminary
H9DP32A4JJBCGR
eNAND 4GB(x8) / Mobile DDR 4Gb(x32, 2CS)
FEATURES
[ CI-MCP ]
Operation Temperature
- (-25)oC ~ 85oC
Package
- 153-ball FBGA - 11.5x13.0mm2, 1.0t, 0.5mm pitch
- Lead & Halogen Free
[ e-NAND ]
[ DDR SDRAM ]
Packaged NAND flash memory with MultiMedia-
Card interface
e-NAND system specification, compliant with
V4.41
Full backward compatibility with previous e-
NAND system specification
Bus mode
- High-speed eMMC protocol.
- Three different data bus widths:
1 bit, 4 bits,8 bits.
- Data transfer rate: up to 104Mbyte/s
- DDR mode supported
Operating voltage range:
- VCCQ = 3.3/1.8V
- VCC = 3.3V
Error free memory access
- Internal error correction code
- Internal enhanced data management
algorithm (Wear levelling, Bad block
management, Garbage collection)
- Possibility for the host to make sudden power
failure safe-update operations for data content
Security
- Password protection of data
- Secure Erase
- Secure Trim
- Secure bad block management
- Write Protection
Boot
- Nomal / Alternative boot sequence method
Power saving
- Enhanced power saving method by
introducing sleep functionality
Partition management with enhanced storage.
Hardware reset supported
Double Data Rate architecture
- two data transfer per clock cycle
x32 bus width
Supply Voltage
- VDD / VDDQ = 1.7 - 1.95 V
Memory Cell Array
- 16Mb x 4Bank x 32 I/O
Bidirectional data strobe (DQS)
Input data mask signal (DQM)
Input Clock
- Differential Clock Inputs (CK, /CK)
MRS, EMRS
- JEDEC Standard guaranteed
CAS Latency
- Programmable CAS latency 2 or 3 supported
Burst Length
- Programmable burst length 2 / 4 / 8 with both sequential
and interleave mode
Rev 0.1 / Nov. 2012
3


3Pages


H9DP32A4JJBCGR-KEM 電子部品, 半導体
Preliminary
H9DP32A4JJBCGR
eNAND 4GB(x8) / Mobile DDR 4Gb(x32, 2CS)
Ball ASSIGNMENT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A ADNU NC
IO0 IO1 IO2
NC
NC
VDDQ
VSSQ
d
VSSd
VDD
VSSQ
d
NC
DNU
B BNC IO3 IO4 IO5 IO6 IO7 DQ30 DQ28 DQ26 DQ24 DQS3 DQ23 VDDQ NC
C CVSSd VDDI A4 VSSm NC VCCQ DQ31 DQ29 DQ27 DQ25 DM3 DQ22 DQ21 VDDQ
D A5 A6 A7 TQ
DQ19
DQ20
VSSQ
d
D
E EA12 A11 A8
NC VCC VSSm NC NC NC
DQ18 DQ17 DQ16
F
VDD A13 A9
VCC
NC
DQS2
DM2
VSSQ
d
F
G CKE0 CS0# NC
VSSm
NC CLK VDDQ VDD
G
H VDDQ RAS# WE#
NC
J CKE1 CAS# CS1#
NC
VSSm
VCC
CLK# VDDQ VSSd
DQS1
DM1
VSSQ
d
H
J
K KBA1 VSSd A10
RST# NC NC VSSm VCC NC
DQ13 DQ14 DQ15
L BA0 A0 A1
DQ11
DQ12
VSSQ
d
L
M MVSSd VDD A2 VCCQ CMD CLK DQ1 DQ3 DQ5 DQ7 DM0 DQ9 DQ10 VDDQ
N NNC
VSSm
A3
VCCQ
VSSm
VSSQ
d
DQ0
DQ2
DQ4
DQ6 DQS0 DQ8 VDDQ
NC
P PDNU
NC VCCQ VSSm VCCQ VSSm NC
VDDQ
VSSQ
d
NC
VDD
VSSQ
d
NC
DNU
1 2 3 4 5 6 7 8 9 10 11 12 13 14
DRAM Commend / Address
DRAM Data IO
Power (DRAM : VDD,VDDQ / eMMC : VCC,VCCQ)
eMMC Command / IO
Ground (DRAM : VSSd,VSSQd / eMMC : VSSm)
Top View
153ball 11.5x13 CI-MCP
(e-NAND X8 + Mobile DDR X32)
Rev 0.1 / Nov. 2012
6

6 Page



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部品番号部品説明メーカ
H9DP32A4JJBCGR-KEM

4GB eNAND Flash(x8) + 4Gb Mobile DDR (x32)

Hynix
Hynix


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