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| Número de pieza | PM0059 | |
| Descripción | Flash programming manual | |
| Fabricantes | STMicroelectronics | |
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PM0059
Programming manual
STM32F205/215, STM32F207/217 Flash programming manual
Introduction
This programming manual describes how to program the Flash memory of STM32F205/215
and STM32F207/217 microcontrollers. For convenience, these will be referred to as
STM32F20x and STM32F21x in the rest of this document unless otherwise specified.
The STM32F20x and STM32F21xembedded Flash memory can be programmed using in-
circuit programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI,
etc.) to download programming data into memory. With IAP, the Flash memory can be re-
programmed while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements a prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out Flash memory operations (program/erase).
Program/erase operations can be performed over the whole product voltage range.
Read/write protections and option bytes are also implemented.
June 2013
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PM0059
1 Glossary
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• The CPU core integrates two debug ports:
– JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
– SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, please refer to the Cortex M3 Technical
Reference Manual
• Word: data/instruction of 32-bit length.
• Half word: data/instruction of 16-bit length.
• Byte: data of 8-bit length.
• Double word: data of 64-bit length.
• IAP (in-application programming): IAP is the ability to reprogram the Flash memory of a
microcontroller while the user program is running.
• ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
• I-Code: this bus connects the Instruction bus of the CPU core to the Flash instruction
interface. Prefetch is performed on this bus.
• D-Code: this bus connects the D-Code bus (literal load and debug access) of the CPU
to the Flash data interface.
• Option bytes: product configuration bits stored in the Flash memory.
• OBL: option byte loader.
• AHB: advanced high-performance bus.
• CPU: refers to the Cortex-M3 core.
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PM0059
Flash memory interface
Note:
Instruction cache memory
To limit the time lost due to jumps, it is possible to retain 64 lines of 128 bits in an instruction
cache memory. This feature can be enabled by setting the instruction cache enable (ICEN)
bit in the FLASH_ACR register. Each time a miss occurs (requested data not present in the
currently used instruction line, in the prefetched instruction line or in the instruction cache
memory), the line read is copied into the instruction cache memory. If some data contained
in the instruction cache memory are requested by the CPU, they are provided without
inserting any delay. Once all the instruction cache memory lines have been filled, the LRU
(least recently used) policy is used to determine the line to replace in the instruction memory
cache. This feature is particularly useful in case of code containing loops.
Data management
Literal pools are fetched from Flash memory through the D-Code bus during the execution
stage of the CPU pipeline. The CPU pipeline is consequently stalled until the requested
literal pool is provided. To limit the time lost due to literal pools, accesses through the AHB
databus D-Code have priority over accesses through the AHB instruction bus I-Code.
If some literal pools are frequently used, the data cache memory can be enabled by setting
the data cache enable (DCEN) bit in the FLASH_ACR register. This feature works like the
instruction cache memory, but the retained data size is limited to 8 rows of 128 bits.
Data in user configuration sector are not cacheable.
2.5
2.5.1
Note:
Erase and program operations
For any Flash memory program operation (erase or program), the CPU clock frequency
(HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a
device reset occurs during a Flash memory operation.
During a write/erase operation to the Flash memory, any attempt to read the Flash memory
will caused the bus to stall. Read operations are processed correctly once the program
operation has completed. This means that code or data fetches cannot be performed while
a write/erase operation is ongoing.
Unlocking the Flash control register
After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the
Flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence is used to unlock this register:
1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
2. Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)
Any wrong sequence will return a bus error and lock up the FLASH_CR register until the
next reset.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the
FLASH_CR register.
The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR
register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall
until the BSY bit is cleared.
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