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PDF LP62S16128C-I Data sheet ( Hoja de datos )
| Número de pieza | LP62S16128C-I | |
| Descripción | 128K X 16 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
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LP62S16128C-I Series
Preliminary
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
April 26, 2002
Remark
Preliminary
PRELIMINARY (April, 2002, Version 0.0)
1
AMIC Technology, Inc.
1 page  
LP62S16128C-I Series
Absolute Maximum Ratings*
VCC to GND ...............................................-0.5V to +4.6V
IN, IN/OUT Volt to GND .................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ....................-40°C to +85°C
Storage Temperature, Tstg......................-55°C to +125°C
Power Dissipation, PT ............................................... 0.7W
*Comments
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol
Parameter
LP62S16128C-55LLI
Min.
Max.
LP62S16128C-70LLI Unit
Min.
Max.
Conditions
ILI Input Leakage Current
-
1
-
1 µA VIN = GND to VCC
ILO
Output Leakage
Current
CE = VIH or
- 1 - 1 µA LB = HB = VIH
VI/O = GND to VCC
Active Power Supply
CE = VIL ,
ICC Current
- 5 - 5 mA LB = VIL or HB = VIL , II/O = 0 mA
-
Min. Cycle, Duty = 100%
ICC1 40 - 35 mA CE = VIL,
Dynamic Operating
LB = VIL or HB = VIL , II/O = 0 mA
Current
CE ≤ 0.2V ,
ICC2 - 15 - 15 mA LB ≤ 0.2V or HB ≤ 0.2V,
f = 1MHz , II/O = 0 mA
ISB - 0.5 - 0.5 mA CE = VIH or LB = HB = VIH
ISB1 Standby Power
Supply Current
- 10 - 10 µA CE ≥ VCC – 0.2V or
LB = HB ≥ VCC – 0.2V,
VIN ≥ VCC – 0.2V or VIN ≤ 0.2V
VOL Output Low Voltage - 0.4 - 0.4 V IOL = 2.1 mA
VOH Output High Voltage
2.2
-
2.2
- V IOH = -1.0 mA
PRELIMINARY (April, 2002, Version 0.0)
5
AMIC Technology, Inc.
5 Page 
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Address
CE
HB, LB
tAS1
WE
DATA IN
DATA OUT
tWHZ4
LP62S16128C-I Series
tWC
tAW
tCW
tBW2
tWP
tDW
tWR3
tDH
tOW
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and , or LB ).
3. tWR is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (April, 2002, Version 0.0)
11
AMIC Technology, Inc.
11 Page | ||
| Páginas | Total 15 Páginas | |
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