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PDF HT82V24 Data sheet ( Hoja de datos )
| Número de pieza | HT82V24 | |
| Descripción | 3-Channel CCD/CIS Analog Signal Processor | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT82V24
16-Bit, 15MSPS, 3-Channel CCD/CIS Analog Signal Processor
Features
· Operating voltage: 5V
· Low power consumption at 380mW (Typ.)
· Power-down mode: Under 2mA (Typ.)
· 16-bit 15 MSPS A/D converter
· Supports ADI/WM mode data output formats selec-
tion
· Guaranteed won¢t miss codes
· 1~6x programmable gain
· Correlated Double Sampling
· ±300mV programmable offset
· Input clamp circuitry
· Internal voltage reference
· Multiplexed byte/nibble-wide output (8´2/4´4 format)
· Programmable 3-wire serial interface
· 3V/5V digital I/O compatibility
· 3-channel operation up to 5 MSPS for each channel
· 2-channel (Even-Odd) operation up to 7.5 MSPS for
each channel
· 1-channel operation up to 15 MSPS
· 20/28-pin SOP/SSOP package (Pb-free on request)
www.DataSheet4UA.cpopmlications
Flatbed document scanners
Film scanners
Digital color copiers
Multifunction peripherals
General Description
The HT82V24 is a complete analog signal processor for
CCD imaging applications. It features a 3-channel archi-
tecture designed to sample and condition the outputs of
tri-linear color CCD arrays. Each channel consists of an
input clamp, Correlated Double Sampler (CDS), offset
DAC and Programmable Gain Amplifier (PGA), and a
high performance 16-bit A/D converter.
The CDS amplifiers may be disabled for use with sen-
sors such as Contact Image Sensors (CIS) and CMOS
active pixel sensors, which do not require CDS.
The 16-bit digital output is multiplexed into an 8/4-bit
output word that is accessed using two/four read cycles.
The internal registers are programmed through a 3-wire
serial interface, which provides gain, offset and operat-
ing mode adjustments. HT82V24 supports ADI/WM
mode data output formats.
The HT82V24 operates from a single 5V power supply,
typically consumes 380mW of power.
Block Diagram
AVD D AVSS R EFT R EFB
AVDD AVSS
DVDD DVSS
V IN R
V IN G
V IN B
O FFSET
CDS +
PG A
9 - B it
DAC
CDS +
9 - B it
DAC
CDS +
In p u t
C la m p
B ia s
9 - B it
DAC
BANDG AP
R e fe re n c e
PG A
3 .1
M UX
1 6 - B it
ADC
16
PG A
6
RED
G REEN
B LU E
C o n fig u r a tio n
R e g is te r
M UX
R e g is te r
G a in
R e g is te r s
9 RED
G REEN
B LU E
O ffs e t
R e g is te r s
C D S C L K 1 /V S M P C D S C L K 2
A D C C LK
OE
8 or4
M UX
DOUT
D ig ita l
C o n tro l
In te rfa c e
S C LK
S LO A D
SD ATA
Rev. 1.00
1 September 7, 2005
1 page  
HT82V24
Functional Description
Integral Nonlinear (INL)
Integral nonlinear error refers to the deviation of each in-
dividual code from a line drawn from zero scale through
a positive full scale. The point used as zero scale occurs
1/2 LSB before the first code transition. A positive full
scale is defined as a level 1/2 LSB beyond the last code
transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinear (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation from this ideal value.
Thus every code must have a finite width. No missing
codes guaranteed for the 16-bit resolution indicates that
all the 65536 codes respectively, are present in the
www.DataSheet4Uo.cveorm-all operating range.
Offset Error
The first ADC code transition should occur at a level 1/2
LSB above the nominal zero scale voltage.
The offset error is the deviation of the actual first code
transition level from the ideal level.
Gain Error
The last code transition should occur for an analog
value of 1/2 LSB below the nominal full-scale voltage.
Gain error is the deviation of the actual difference be-
tween the first and the last code transitions and the ideal
difference between the first and the last code transi-
tions.
Sampling Delay
The sampling delay is the time delay that occurs when a
sampling edge is applied to the HT82V24 until the actual
sample of the input signal is held. Both CDSCLK1 and
CDSCLK2 sample the input signal during the transition
from high to low, so the sampling delay is measured
from each clock¢s falling edge to the instant the actual
internal sample is taken.
Internal Register Descriptions
Register
Name
Address
A2 A1 A0
Configuration 0 0 0
MUX
001
Red PGA
010
Green PGA 0 1 1
Blue PGA
100
Red Offset
1
0
1
Green Offset 1 1 0
Blue Offset
1
1
1
Data Bits
D8 D7 D6 D5 D4
D3
0
Don¢t care
3-CH CDS on
Clamp
Voltage
0
RGB/
BGR
Red
Green
0 0 0 MSB
0 0 0 MSB
0 0 0 MSB
MSB
MSB
MSB
Blue
Internal Register Map (ADI Mode)
0
D2 D1 D0
Enable
Power
Down
Input
Range
1 byte
out
000
LSB
LSB
LSB
LSB
LSB
LSB
Register
Name
Configuration
MUX
Red PGA
Green PGA
Blue PGA
Red Offset
Green Offset
Blue Offset
Address
A2 A1 A0
000
001
010
011
100
101
110
111
Data Bits
D8 D7 D6 D5 D4 D3 D2 D1 D0
1
Clamp Timing
Control
3-CH
CDS on
Clamp
Voltage
Enable
Power
Down
Input
Range
Output
Format
DEL
RGB/
BGR
Red
Green
Blue POSNNEG
VDEL
0 0 0 MSB
LSB
0 0 0 MSB
LSB
0 0 0 MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Internal Register Map (Wolfson Mode)
Rev. 1.00
5 September 7, 2005
5 Page 
HT82V24
A n a lo g In p u t
C D S C LK 1
C D S C LK 2
P ix e l ( N )
tA D
tA D
tC 1 tC 2 C 1
tC 1 C 2
tC 2
tC 2 A D R
tC 2 A D F
P ix e l ( N + 1 )
tP R A
A D C C LK
O u tp u t D a ta
D 7~D 0
P ix e l ( N - 9 )
H ig h B y te
www.DataSheet4U.com
A n a lo g In p u t
(R , G , B )
C D S C LK 2
tA D C L K
P ix e l ( N - 9 )
L o w B y te
tA D C L K
tO D
P ix e l ( N - 8 )
H ig h B y te
P ix e l ( N - 8 )
L o w B y te
1-Channel CDS Mode Timing
P ix e l ( N - 7 )
H ig h B y te
P ix e l ( N + 2 )
tA D
tC 2
tC 2 A D
P ix e l ( N + 3 )
tP R A
P ix e l ( N + 2 )
P ix e l ( N - 7 )
L o w B y te
A D C C LK
O u tp u t D a ta
D 7~D 0
tA D C L K
tA D C 2
tC 2 A D R
tA D C L K
tO D
R (N -2 ) G (N -2 ) G (N -2 ) B (N -2 ) B (N -2 ) R (N -1 ) R (N -1 ) G (N -1 ) G (N -1 ) B (N -1 ) B (N -1 ) R (N ) R (N ) G (N ) G (N )
H ig h L o w H ig h L o w H ig h L o w H ig h L o w H ig h L o w H ig h L o w H ig h L o w
B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te B y te
3-Channel SHA Mode Timing
A n a lo g In p u t
(R , G , B )
P ix e l ( N + 3 )
tA D
P ix e l ( N + 4 )
C D S C LK 2
A D C C LK
O u tp u t D a ta
D 7~D 0
tC 2
tA D C 2
tC 2 A D R
tC 2 A D F
tA D C L K
tA D C L K
G (N -2 )
H ig h
B y te
G (N -2 )
Low
B y te
B (N -2 )
H ig h
B y te
B (N -2 )
Low
B y te
G (N -1 )
H ig h
B y te
G (N -1 )
Low
B y te
2-Channel SHA Mode Timing
B (N -1 )
H ig h
B y te
B (N -1 )
Low
B y te
G (N )
H ig h
B y te
G (N )
Low
B y te
Rev. 1.00
11 September 7, 2005
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet HT82V24.PDF ] | |
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