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PDF ISL9016 Data sheet ( Hoja de datos )
| Número de pieza | ISL9016 | |
| Descripción | 150mA Dual LDO | |
| Fabricantes | Intersil Corporation | |
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150mA Dual LDO with Low Noise, High PSRR, and Low IQ
ISL9016
Features
ISL9016 is a high performance dual LDO capable of providing
up to 150mA current on each channel. It features a low standby
current and very high PSRR and is stable with output
capacitance of 1µF to 4.7µF with an ESR of up to 200mΩ.
The device integrates a separate enable function for each
output. The quiescent current is typically 49µA when only one
LDO is enabled and typically 80µA when both LDOs are
enabled. When both LDOs are under shutdown condition, the
drawing current is typically less than 1µA.
ISL9016 provides a wide input voltage range from 1.8V to
6.5V. It also has a high PSRR of 80dB at 1kHz and 45dB at
1MHz. ISL9016 also provides output current limit, overheat
protection, reverse current protection, as well as excellent load
transient response.
ISL9016 is offered in a tiny 1.6mmx1.6mm 6 Ld µTDFN
package. Output voltage options are available from 1.2V to
3.3V. Several combinations of voltage outputs are standard
and others may be available upon request.
• Dual Integrated 150mA High Performance LDOs
• High PSRR: 80dB @ 1kHz and 45dB @ 1MHz
• Reverse Current Protection
• Low Quiescent Current
- 49µA (Single LDO Enabled)/80µA (Dual LDOs Enabled)
• Excellent Load Transient Response
• Typically ±0.8% Output Voltage Accuracy
• Low Output Noise: Typically 25µVRMS
• Wide Input Voltage Capability: 1.8V to 6.5V
• Low Dropout Voltage: Typically 120mV @ 150mA
• Separate Enable Control for each LDO
• Stable with 1µF to 4.7µF Ceramic Output Capacitors
• Soft-start to Limit Input Current Surge During Enable
• Current Limit and Overheat Protection
• Tiny 6 Ld 1.6mmx1.6mm µTDFN package
• Pb-free (RoHS Compliant)
Applications
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3/4 Players, PMP, DSC
• Handheld Devices including Medical Handhelds
VIN (1.8V TO 6.5V)
ISL9016
VIN VOUT1
GND
VOUT2
C1
EN2
EN1
R1 ON
ON
OFF
OFF
C1, C2, C3: 1µF, X5R (or X7R) CERAMIC CAPACITOR
R1, R2: 100k
C2
R2
FIGURE 1. TYPICAL APPLICATION DIAGRAM
VOUT1
1.2V~3.3V, 0~150mA
VOUT2
1.2V~3.3V, 0~150mA
C3
May 16, 2011
FN6832.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL9016
Electrical Specifications Typical specifications are measured at the following conditions: TA = +25°C; VIN = (VO + 0.5V) to 6.5V with a
minimum VIN of 1.8V; CIN = 1µF; CO = 1µF. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 8) TYP (Note 8) UNITS
EN PIN CHARACTERISTICS
Input Low Voltage
VIL
Input High Voltage
VIH
Input Leakage Current
IIL, IIH
REVERSE CURRENT CHARACTERISTICS
TA = -20°C to +85°
-0.3 0.4 V
1.1 VIN + 0.3 V
0.1 µA
Output Reverse Leakage Current
(Note 7)
IORLC VIN = 0V, VOUT = 5.5V
8 15 µA
NOTES:
6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.80V.
7. Output reverse leakage current is measured with VIN pin grounded and VOUT pin connected to 5.5V.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5 FN6832.1
May 16, 2011
5 Page 
ISL9016
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
E AB
64
A
PIN 1
REFERENCE
2X 0.15 C
1
2X 0.15 C
3
TOP VIEW
D
A1
e
1.00 REF
46
L
D2 CO.2
3
E2
DAP SIZE 1.30 x 0.76
1 b 6X
0.10 M C A B
BOTTOM VIEW
0.10 C
DETAIL A
6X 0.08 C
SIDE VIEW
A3 C
SEATING
PLANE
L6.1.6x1.6A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN NOMINAL MAX
NOTES
A
0.45 0.50 0.55
-
A1 - - 0.05 -
A3 0.127 REF -
b
0.15 0.20 0.25
-
D
1.55 1.60 1.65
4
D2 0.40 0.45 0.50 -
E
1.55 1.60 1.65
4
E2 0.95 1.00 1.05 -
e
0.50 BSC
-
L
0.25 0.30 0.35
-
NOTES:
Rev. 1 6/06
1. Dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.
3. Warpage shall not exceed 0.10mm.
4. Package length/package width are considered as special
characteristics.
5. JEDEC Reference MO-229.
6. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.127±0.008
A1
DETAIL A
0.50
0.25
0.127 +0.058
-0.008
TERMINAL THICKNESS
1.00
1.25
0.45 1.00
0.30
2.00
LAND PATTERN 6
11 FN6832.1
May 16, 2011
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL9016.PDF ] | |
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