PDF AS7C3364NTF36B Data sheet ( Hoja de datos )

Número de pieza	AS7C3364NTF36B
Descripción	(AS7C3364NTF32B / AS7C3364NTF36B) 3.3V 64K x 32/36 Flowthrough Synchronous SRAM
Fabricantes	Alliance Semiconductor Corporation
Logotipo
Hay una vista previa y un enlace de descarga de AS7C3364NTF36B (archivo pdf) en la parte inferior de esta página. Total 19 Páginas
No Preview Available ! April 2005 AS7C3364NTF32B AS7C3364NTF36B ® 3.3V 64K × 32/36 Flowthrough Synchronous SRAM with NTDTM Features • Organization: 65,536 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock to data access: 7.5/8.0/10.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable control • Available in 100-pin TQFP package www.DataShee•t4BU.yctoemwrite enables • Clock enable for operation hold Logic block diagram A[15:0] 16 CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ DQ Aredgdirsetesrs Burst logic CLK Control logic CLK DQ[a,b,c,d] 32/36 D Data Input Q Register CLK • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation 16 DQ Write delay addr. registers CLK 16 CLK 32/36 64K x 32/36 SRAM Array 32/36 32/36 32/36 CLK CEN Output Buffer OE 32/36 OE DQ[a,b,c,d] Selection guide -75 -80 -10 Units Minimum cycle time 8.5 10 12 ns Maximum clock access time 7.5 8.0 10 ns Maximum operating current 260 230 200 mA Maximum standby current 110 100 90 mA Maximum CMOS standby current (DC) 30 30 30 mA 4/28/05, v 1.0 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C3364NTF32B/36B ® Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked. A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted. DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0, CE1, CE2 I SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is high. www.DataSheetA4UD.cVom/LD I SYNC Advance or Load. When sampled high, the internal burst address counter will increment in the order defined by the LBO input value. When low, a new address is loaded. R/W I SYNC A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD is high. BW[a,b,c,d] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive. LBO I STATIC Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. Burst order Interleaved burst order LBO = 1 A1 A0 A1 A0 A1 A0 Starting address 00 01 10 First increment 01 00 11 Second increment 1 0 1 1 0 0 Third increment 1 1 1 0 0 1 A1 A0 11 10 01 00 Linear burst order LBO = 0 A1 A0 A1 A0 A1 A0 Starting Address 0 0 0 1 1 0 First increment 01 10 11 Second increment 1 0 1 1 0 0 Third increment 1 1 0 0 0 1 A1 A0 11 00 01 10 4/28/05, v 1.0 Alliance Semiconductor P. 5 of 19 5 Page Timing waveform of write cycle CLK tCENS tCENH CEN www.DataSheet4U.com Address tAS tAH A1 A2 ® tCH tCL AS7C3364NTF32B/36B tCYC A3 R/W BWn tCSS tCSH CE0,CE2 CE1 ADV/LD tADVS tADVH OE Din Dout D(A1) tHZOE Q(n-1) D(A2) D(A2Y‘01) D(A2Y‘10) tDS tDH D(A3) D(A2Y‘11) D(A3Y‘01) Command WRITE DSEL D(A1) WRITE D(A2) BURST BURST BURST STALL WRITE WRITE WRITE D(A2Ý01) D(A2Ý10) D(A2Ý11) WRITE D(A3) BURST WRITE D(A3Ý01) 4/28/05, v 1.0 Alliance Semiconductor P. 11 of 19 11 Page

Páginas	Total 19 Páginas
PDF Descargar	[ Datasheet AS7C3364NTF36B.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AS7C3364NTF36B	(AS7C3364NTF32B / AS7C3364NTF36B) 3.3V 64K x 32/36 Flowthrough Synchronous SRAM	Alliance Semiconductor Corporation

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar