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PDF AS7C332MPFD18A Data sheet ( Hoja de datos )

Número de pieza AS7C332MPFD18A
Descripción 3.3V 2M x 18 pipelined burst synchronous SRAM
Fabricantes Alliance Semiconductor Corporation 
Logotipo Alliance Semiconductor Corporation Logotipo



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No Preview Available ! AS7C332MPFD18A Hoja de datos, Descripción, Manual

February 2005
AS7C332MPFD18A
®
3.3V 2M × 18 pipelined burst synchronous SRAM
Features
• Organization: 2,097,152 words × 18 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.1/3.5/3.8 ns
• Fast OE access time: 3.1/3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
www.DataSheet4IUn.dciovmidual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[20:0]
21
GWE
BWb
BWE
BWa
CCEE01
CE2
ZZ
Power
down
OE
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
LBO
CLK
CS Burst logic
CLR
DQ
CS
Address
register
21
CLK
19 21
2M x 18
Memory
array
18 18
D DQb Q
Byte Write
registers
CLK
D DQa Q
BreygteisWterritse
CLK
D Enable Q
register
CE
CLK
D Enable Q
redgeilsatyer
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ[a,b]
-200 -166
56
200 166
3.1 3.5
450 400
170 150
90 90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
2/10/05, v.1.1
Alliance Semiconductor
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.

1 page




AS7C332MPFD18A pdf
AS7C332MPFD18A
®
Signal descriptions
Pin
CLK
A,A0,A1
DQ[a,b]
CE0
CE1, CE2
www.DataSheet4U.cAoDmSP
ADSC
ADV
GWE
BWE
BW[a,b]
OE
LBO
ZZ
NC
I/O Properties
Description
I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
I/O SYNC Data. Driven as output when the chip is enabled and when OE is active.
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
I
SYNC
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
I SYNC Address strobe processor. Asserted low to load a new address or to enter standby mode.
I SYNC Address strobe controller. Asserted low to load a new address or to enter standby mode.
I SYNC Advance. Asserted low to continue burst read/write.
I
SYNC
Global write enable. Asserted low to write all 18 bits. When high, BWE and BW[a,b] control write
enable.
I SYNC Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
I SYNC BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive,
the cycle is a read cycle.
I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
I
STATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order. This signal is internally pulled High.
I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
- - No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
2/10/05, v.1.1
Alliance Semiconductor
5 of 19

5 Page





AS7C332MPFD18A arduino
AS7C332MPFD18A
Key to switching waveforms
®
Rising input
Falling input
don’t care
Timing waveform of read cycle
CLK
www.DataSheet4U.com tADSPS
ADSP
tADSPH
tCYC
tCH tCL
ADSC
tADSCS
tADSCH
tAS tAH
Address
A1
A2
LOAD NEW ADDRESS
A3
GWE, BWE
tWS tWH
tCSS
CE0, CE2
tCSH
Undefined
CE1
ADV
OE
Dout
tADVS
tADVH
ADV inserts wait states
tOE
tLZOE
Q(A1)
tHZOEtOH
Q(A2)
tCD
Q(A2Ý01)
Q(A2Ý10)
tHZC
Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10)
Read
Q(A1)
Suspend
Read
Q(A1)
Read Burst Burst Suspend Burst Read Burst
Burst
Burst
Q(A2) Read Read
Read
Read Q(A3) Read
Read
Read DSEL*
Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11)
Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
*Outputs are disabled within two clk cycles after DSEL command
2/10/05, v.1.1
Alliance Semiconductor
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