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PDF LPC2106 Data sheet ( Hoja de datos )
| Número de pieza | LPC2106 | |
| Descripción | Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC2104/2105/2106
Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with
64 kB/32 kB/16 kB RAM
Rev. 04 — 05 February 2004
Product data
1. General description
The LPC2104, 2105 and 2106 are based on a 16/32 bit ARM7TDMI-S CPU with
real-time emulation and embedded trace support, together with 128 kbytes (kB) of
embedded high speed flash memory. A 128 bit wide memory interface and a unique
accelerator architecture enable 32 bit code execution at maximum clock rate. For
critical code size applications, the alternative 16-bit Thumb Mode reduces code by
more than 30% with minimal performance penalty.
Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip
SRAM options up to 64 kilobytes, they are very well suited for communication
gateways and protocol converters, soft modems, voice recognition and low end
imaging, providing both large buffer size and high processing power. Various 32 bit
timers, PWM channels and 32 GPIO lines make these microcontrollers particularly
suitable for industrial control and medical systems.
2. Features
2.1 Key features
s 16/32 bit ARM7TDMI-S processor.
s 16/32/64 kB on-chip Static RAM.
s 128 kB on-chip Flash Program Memory. 128 bit wide interface/accelerator
enables high speed 60 MHz operation.
s In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot-loader software. Flash programming takes 1 ms per 512 byte line. Single
sector or full chip erase takes 400 ms.
s Vectored Interrupt Controller with configurable priorities and vector addresses.
s EmbeddedICE-RT interface enables breakpoints and watchpoints. Interrupt
service routines can continue to execute whilst the foreground task is debugged
with the on-chip RealMonitor software.
s Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of
instruction execution.
s Multiple serial interfaces including two UARTs (16C550), Fast I2C (400 kbits/s)
and SPI.
s Two 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time
Clock and Watchdog.
s Up to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48
(7 × 7 mm2) package.
1 page  
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
5.2 Pin description
Table 3: Pin description
Symbol
Pin
Type
P0.0 to P0.31
13, 14, 18,
21-24, 28-30,
35-37, 41,
44-48, 1-3,
32-34, 38,
39, 8-10, 15,
16
I/O
13 I/O
O
O
14 I/O
I
O
18 I/O
I/O
I
21 I/O
I/O
O
22 I/O
I/O
I
23 I/O
I/O
O
24 I/O
I/O
I
28 I/O
I
O
29 I/O
O
O
Description
Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction
controls for each bit. The operation of port 0 pins depends upon the pin
function selected via the Pin Connect Block.
P0.0 — Port 0 bit 0.
TxD0 — Transmitter output for UART 0.
PWM1 — Pulse Width Modulator output 1.
P0.1 — Port 0 bit 1.
RxD0 — Receiver input for UART 0.
PWM3 — Pulse Width Modulator output 3.
P0.2 — Port 0 bit 2.
SCL — I2C clock input/output. Open drain output (for I2C compliance).
CAP0.0 — Capture input for Timer 0, channel 0.
P0.3 — Port 0 bit 3.
SDA — I2C data input/output. Open drain output (for I2C compliance).
MAT0.0 — Match output for Timer 0, channel 0.
P0.4 — Port 0 bit 4.
SCK — Serial clock. SPI clock output from master or input to slave.
CAP0.1 — Capture input for Timer 0, channel 1.
P0.5 — Port 0 bit 5.
MISO — Master In Slave Out. Data input to SPI master or data output from
SPI slave.
MAT0.1 — Match output for Timer 0, channel 1.
P0.6 — Port 0 bit 6.
MOSI — Master Out Slave In. Data output from SPI master or data input to
SPI slave.
CAP0.2 — Capture input for Timer 0, channel 2.
P0.7 — Port 0 bit 7.
SSEL — Slave Select. Selects the SPI interface as a slave.
PWM2 — Pulse Width Modulator output 2.
P0.8 — Port 0 bit 8.
TxD1 — Transmitter output for UART 1.
PWM4 — Pulse Width Modulator output 4.
9397 750 12792
Product data
Rev. 04 — 05 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 32
5 Page 
Philips Semiconductors
4.0 GB
3.75 GB
3.5 GB
3.0 GB
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
AHB PERIPHERALS
VPB PERIPHERALS
RESERVED ADDRESS SPACE
0xFFFF FFFF
0xF000 0000
0xEFFF FFFF
0xE000 0000
0xDFFF FFFF
0xC000 0000
2.0 GB
1.0 GB
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY
RESERVED ADDRESS SPACE
64 KBYTE ON-CHIP STATIC RAM
0x8000 0000
0x7FFF FFFF
0x7FFF E000
0x7FFF DFFF
0x4001 0000
0x4000 FFFF
0x4000 0000
0x3FFF FFFF
RESERVED ADDRESS SPACE
0.0 GB
128 KBYTE ON-CHIP FLASH MEMORY
Fig 5. LPC2106 memory map.
0x0002 0000
0x0001 FFFF
0x0000 0000
002aaa413
6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes, them as FIQ, vectored IRQ, and non-vectored IRQ as defined by
programmable settings. The programmable assignment scheme means that priorities
of interrupts from the various peripherals can be dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is
assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the
ARM processor. The fastest possible FIQ latency is achieved when only one request
is classified as FIQ, because then the FIQ service routine can simply start dealing
with that device. But if more than one request is assigned to the FIQ class, the FIQ
service routine can read a word from the VIC that identifies which FIQ source(s) is
(are) requesting an interrupt.
9397 750 12792
Product data
Rev. 04 — 05 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 32
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