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PDF LT1167AI Data sheet ( Hoja de datos )
| Número de pieza | LT1167AI | |
| Descripción | Single Resistor Gain Programmable/ Precision Instrumentation Amplifier | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Single Gain Set Resistor: G = 1 to 10,000
s Gain Error: G = 10, 0.08% Max
s Gain Nonlinearity: G = 10, 10ppm Max
s Input Offset Voltage: G = 10, 60µV Max
s Input Offset Voltage Drift: 0.3µV/°C Max
s Input Bias Current: 350pA Max
s PSRR at G = 1: 105dB Min
s CMRR at G = 1: 90dB Min
s Supply Current: 1.3mA Max
s Wide Supply Range: ±2.3V to ±18V
s 1kHz Voltage Noise: 7.5nV/√Hz
s 0.1Hz to 10Hz Noise: 0.28µVP-P
s Available in 8-Pin PDIP and SO Packages
s Meets IEC 1000-4-2 Level 4 ESD Tests with
Two External 5k Resistors
U
APPLICATIONS
s Bridge Amplifiers
s Strain Gauge Amplifiers
s Thermocouple Amplifiers
s Differential to Single-Ended Converters
s Medical Instrumentation
LT1167
Single Resistor Gain
Programmable, Precision
Instrumentation Amplifier
DESCRIPTION
The LT®1167 is a low power, precision instrumentation
amplifier that requires only one external resistor to set gains
of 1 to 10,000. The low voltage noise of 7.5nV/√Hz (at 1kHz)
is not compromised by low power dissipation (0.9mA typical
for ±2.3V to ±15V supplies).
The high accuracy of 10ppm maximum nonlinearity and
0.08% max gain error (G = 10) is not degraded even for load
resistors as low as 2k (previous monolithic instrumentation
amps used 10k for their nonlinearity specifications). The
LT1167 is laser trimmed for very low input offset voltage
(40µV max), drift (0.3µV/°C), high CMRR (90dB, G = 1) and
PSRR (105dB, G = 1). Low input bias currents of 350pA max
are achieved with the use of superbeta processing. The
output can handle capacitive loads up to 1000pF in any gain
configuration while the inputs are ESD protected up to 13kV
(human body). The LT1167 with two external 5k resistors
passes the IEC 1000-4-2 level 4 specification.
The LT1167, offered in 8-pin PDIP and SO packages, requires
significantly less PC board area than discrete multi op amp
and resistor designs. These advantages make the LT1167 the
most cost effective solution for precision instrumentation
amplifier applications.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
Single Supply Barometer
VS
R5
392k
LT1634CCZ-1.25
1
2
R4
50k
R3
50k
3+ 8
1/2
LT1490
2– 4
1
R6
1k
5+
1/2
LT1490
R8 6 –
100k
LUCAS NOVA SENOR
NPC-1220-015-A-3L
4 –1
5k 5k
2 5k
5k
6
RSET
+3
5
7
2–
1
VS
7
R1
825Ω
LT1167
R2 G = 60
12Ω 8
3+
4
R7
50k 0.2% ACCURACY AT 25°C
1.2% ACCURACY AT 0°C TO 60°C
VS = 8V TO 30V
6
5
TO
4-DIGIT
DVM
VOLTS
2.800
3.000
3.200
INCHES Hg
28.00
30.00
32.00
1167 TA01
Gain Nonlinearity
G = 1000
RL = 1k
VOUT = ±10V
OUTPUT VOLTAGE (2V/DIV)
1167 TA02
1
1 page  
LT1167
ELECTRICAL CHARACTERISTICS
VS = ±15V, VCM = 0V, – 40°C ≤ TA ≤ 85°C, RL = 2k, unless otherwise noted. (Note 4)
SYMBOL
GN
G/T
VOST
VOSI
VOSIH
VOSO
VOSOH
VOSI / T
VOSO/ T
IOS
IOS/T
IB
IB/T
VCM
CMRR
PSRR
IS
VOUT
IOUT
SR
VREF
PARAMETER
Gain Error
Gain Nonlinearity (Notes 2, 4)
Gain vs Temperature
Total Input Referred
Offset Voltage
Input Offset Voltage
Input Offset Voltage Hysteresis
Output Offset Voltage
Output Offset Voltage Hysteresis
Input Offset Drift (RTI)
Output Offset Drift
Input Offset Current
Input Offset Current Drift
Input Bias Current
Input Bias Current Drift
Input Voltage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Supply Current
Output Voltage Swing
Output Current
Slew Rate
REF Voltage Range
CONDITIONS (Note 7)
G=1
G = 10 (Note 2)
G = 100 (Note 2)
G = 1000 (Note 2)
VO = ±10V, G = 1
VO = ±10V, G = 10 and 100
VO = ±10V, G = 1000
G < 1000 (Note 2)
VOST = VOSI + VOSO/G
(Notes 3, 6)
(Notes 3, 6)
(Note 3)
(Note 3)
VS = ±2.3V to ±5V
VS = ±5V to ±18V
1k Source Imbalance,
VCM = 0V to ±10V
G=1
G = 10
G = 100
G = 1000
VS = ±2.3V to ±18V
G=1
G = 10
G = 100
G = 1000
VS = ±2.3V to ±5V
VS = ±5V to ±18V
G = 1, VOUT = ±10V
(Note 3)
LT1167AI
MIN TYP MAX
q 0.014 0.04
q 0.130 0.40
q 0.140 0.40
q 0.160 0.40
q 2 15
q 5 20
q 26 70
q 20 50
LT1167I
MIN TYP MAX
0.015
0.140
0.150
0.180
0.05
0.42
0.42
0.45
3 20
6 30
30 100
20 50
UNITS
%
%
%
%
ppm
ppm
ppm
ppm/°C
q 20 75
25 100
µV
3.0 3.0 µV
q 180 500
200 600
µV
30 30 µV
q 0.05 0.3
0.06 0.4
µV/°C
q 0.8 5
1 6 µV/°C
q 110 550
120 700
pA
q 0.3
0.3 pA/°C
q 180 600
220 800
pA
q 0.5
0.6 pA/°C
q – VS + 2.1
q – VS + 2.1
+ VS – 1.3 – VS + 2.1
+ VS – 1.4 – VS + 2.1
+VS – 1.3
+ VS – 1.4
V
V
q 86 90
q 98 105
q 114 118
q 116 133
81 90
95 105
112 118
112 133
dB
dB
dB
dB
q 100 112
q 120 125
q 125 132
q 128 140
95 112
115 125
120 132
125 140
q 1.1 1.6
1.1 1.6
q – VS + 1.4
q – VS + 1.6
+ VS – 1.3 – VS + 1.4
+ VS – 1.5 – VS + 1.6
+ VS – 1.3
+ VS – 1.5
q 15 20
15 20
q 0.55 0.95
0.55 0.95
q – VS + 1.6
+ VS – 1.6 – VS + 1.6
+ VS – 1.6
dB
dB
dB
dB
mA
V
V
mA
V/µs
V
The q denotes specifications that apply over the full specified
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be imparied.
Note 2: Does not include the effect of the external gain resistor RG.
Note 3: This parameter is not 100% tested.
Note 4: The LT1167AC/LT1167C are designed, characterized and expected
to meet the industrial temperature limits, but are not tested at – 40°C and
85°C. I-grade parts are guaranteed.
Note 5: This parameter is measured in a high speed automatic tester that
does not measure the thermal effects with longer time constants. The
magnitude of these thermal effects are dependent on the package used,
heat sinking and air flow conditions.
Note 6: Hysteresis in offset voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Offset voltage hysteresis is always measured at 25°C, but
the IC is cycled to 85°C I-grade (or 70°C C-grade) or – 40°C I-grade
(0°C C-grade) before successive measurement. 60% of the parts will
pass the typical limit on the data sheet.
Note 7: Typical parameters are defined as the 60% of the yield parameter
distribution.
5
5 Page 
LT1167
BLOCK DIAGRAM
V+
–IN 2
R3
400Ω
V–
RG 1
RG 8
V+
+IN 3
R4
400Ω
V–
VB
+
A1
–
C1
Q1
R1
24.7k
VB
+
A2
–
C2
Q2
R2
24.7k
R5 R6
10k 10k
6 OUTPUT
–
A3
+
V–
R7 R8
10k 10k
5 REF
V–
7 V+
4 V–
PREAMP STAGE
DIFFERENCE AMPLIFIER STAGE
Figure 1. Block Diagram
1167 F01
U
THEORY OF OPERATIO
The LT1167 is a modified version of the three op amp
instrumentation amplifier. Laser trimming and monolithic
construction allow tight matching and tracking of circuit
parameters over the specified temperature range. Refer to
the block diagram (Figure 1) to understand the following
circuit description. The collector currents in Q1 and Q2 are
trimmed to minimize offset voltage drift, thus assuring a
high level of performance. R1 and R2 are trimmed to an
absolute value of 24.7k to assure that the gain can be set
accurately (0.05% at G = 100) with only one external
resistor RG. The value of RG in parallel with R1 (R2)
determines the transconductance of the preamp stage. As
RG is reduced for larger programmed gains, the transcon-
ductance of the input preamp stage increases to that of the
input transistors Q1 and Q2. This increases the open-loop
gain when the programmed gain is increased, reducing
the input referred gain related errors and noise. The input
voltage noise at gains greater than 50 is determined only
by Q1 and Q2. At lower gains the noise of the difference
amplifier and preamp gain setting resistors increase the
noise. The gain bandwidth product is determined by C1,
C2 and the preamp transconductance which increases
with programmed gain. Therefore, the bandwidth does not
drop proportional to gain.
The input transistors Q1 and Q2 offer excellent matching,
which is inherent in NPN bipolar transistors, as well as
picoampere input bias current due to superbeta process-
ing. The collector currents in Q1 and Q2 are held constant
due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop which in turn impresses the differential
input voltage across the external gain set resistor RG.
Since the current that flows through RG also flows through
R1 and R2, theratios provide a gained-up differential volt-
age,G = (R1 + R2)/RG, to the unity-gain difference amplifier
A3. The common mode voltage is removed by A3, result-
ing in a single-ended output voltage referenced to the
voltage on the REF pin. The resulting gain equation is:
VOUT – VREF = G(VIN+ – VIN–)
where:
G = (49.4kΩ / RG) + 1
solving for the gain set resistor gives:
RG = 49.4kΩ /(G – 1)
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LT1167AI.PDF ] | |
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