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PDF LTC2430 Data sheet ( Hoja de datos )
| Número de pieza | LTC2430 | |
| Descripción | (LTC2430 / LTC2431) 20-Bit No Latency Delta-Sigma ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2430/LTC2431
20-Bit No Latency ∆ΣTM ADCs
with Differential Input and
Differential Reference
FEATURES
s Low Supply Current (200µA in Conversion Mode
and 4µA in Autosleep Mode)
s Differential Input and Differential Reference
with GND to VCC Common Mode Range
s 3ppm INL, No Missing Codes
s 10ppm Full-Scale Error and 1ppm Offset
s 0.56ppm Noise, 20.8 ENOBs
s No Latency: Digital Filter Settles in a Single Cycle.
Each Conversion Is Accurate, Even After an
Input Step
s Single Supply 2.7V to 5.5V Operation
s Internal Oscillator—No External Components
Required
s 110dB Min, 50Hz/60Hz Notch Filter
s Pin Compatible with 24-Bit LTC2410/LTC2411
U
APPLICATIO S
s Direct Sensor Digitizer
s Weight Scales
s Direct Temperature Measurement
s Gas Analyzers
s Strain Gauge Transducers
s Instrumentation
s Data Acquisition
s Industrial Process Control
s DVMs and Meters
DESCRIPTIO
The LTC®2430/LTC2431 are 2.7V to 5.5V micropower
20-bit differential ∆Σ analog-to-digital converters with an
integrated oscillator, 3ppm INL and 0.56ppm RMS noise.
They use delta-sigma technology and provide single cycle
settling time for multiplexed applications. Through a
single pin, the LTC2430/LTC2431 can be configured for
better than 110dB differential mode rejection at 50Hz or
60Hz ±2%, or they can be driven by an external oscillator
for a user-defined rejection frequency. The internal oscil-
lator requires no external frequency setting components.
The converters accept any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The full-
scale differential input range is from – 0.5VREF to 0.5VREF.
The reference common mode voltage, VREFCM, and the
input common mode voltage, VINCM, may be indepen-
dently set anywhere within GND to VCC. The DC common
mode input rejection is better than 120dB.
The LTC2430/LTC2431 communicate through a flexible
3-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
TYPICAL APPLICATIO S
VOUT
3V TO 5V
4.7µF
0.1µF
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
(VOUT + 0.25V) TO 20V
64
LT1790
12
0.1µF
VCC FO
LTC2431
REF+
SCK
REF–
IN+
IN–
GND
SDO
CS
24301 TA01
VCC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
3-WIRE
SPI INTERFACE
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
5
VCC = 5V
4 VREF = 5V
3
VINCM = VINCM = 2.5V
FO = GND
2
25°C
1
85°C
0
–1 –45°C
–2
–3
–4
–5
–2.5 –2 –1.5 –1 – 0.5 0 0.5 1 1.5 2 2.5
INPUT VOLTAGE (V)
24301 G01
24301f
1
1 page  
LTC2430/LTC2431
WU
TI I G CHARACTERISTICS The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
fEOSC
tHEO
tLEO
tCONV
fISCK
DISCK
fESCK
tLESCK
tHESCK
tDOUT_ISCK
tDOUT_ESCK
t1
t2
t3
t4
tKQMAX
tKQMIN
t5
t6
PARAMETER
CONDITIONS
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
Internal SCK Duty Cycle
(Note 10)
External SCK Frequency Range
(Note 9)
External SCK Low Period
(Note 9)
External SCK High Period
(Note 9)
Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
External SCK 24-Bit Data Output Time (Note 9)
CS ↓ to SDO Low Z
CS ↑ to SDO High Z
CS ↓ to SCK ↓
(Note 10)
CS ↓ to SCK ↑
(Note 9)
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
(Note 5)
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
MIN TYP MAX
q5
2000
q 0.25
200
q 0.25
200
q 130.86 133.53 136.20
q 157.03 160.23 163.44
q 20510/fEOSC (in kHz)
19.2
fEOSC/8
q 45
55
q 2000
q 250
q 250
q 1.22
1.25 1.28
q 192/fEOSC (in kHz)
q 24/fESCK (in kHz)
q0
200
q0
200
q0
200
q 50
q 220
q 15
q 50
q 50
UNITS
kHz
µs
µs
ms
ms
ms
kHz
kHz
%
kHz
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is calculated as the measured code minus the
expected value.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
24301f
5
5 Page 
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
Converter Operation Cycle
The LTC2430/LTC2431 are low power, delta-sigma analog-
to-digital converters with an easy-to-use 3-wire serial inter-
face (see Figure 1). Their operation is made up of three states.
The converters’ operating cycle begins with the conversion,
followed by the low power sleep state and ends with the data
output (see Figure 2). The 3-wire interface consists of serial
data output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2430/LTC2431 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as
CS is HIGH. While in this sleep state, power consumption
is reduced by nearly two orders of magnitude. The conver-
sion result is held indefinitely in a static shift register while
the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low power mode
and enters the data output state. If CS is pulled HIGH be-
fore the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still held
in the internal static shift register. If CS remains LOW after
the first rising edge of SCK, the device begins outputting
the conversion result. Taking CS high at this point will
terminate the data output state and start a new conversion.
There is no latency in the conversion result. The data out-
put corresponds to the conversion just performed. This
result is shifted out on the serial data out pin (SDO) under
the control of the serial clock (SCK). Data is updated on the
CONVERT
SLEEP
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
2431 F02
Figure 2. LTC2430/LTC2431 State Transition Diagram
falling edge of SCK allowing the user to reliably latch data
on the rising edge of SCK (see Figure 3). The data output
state is concluded once 24 bits are read out of the ADC or
when CS is brought HIGH. The device automatically initiates
a new conversion and the cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2430/LTC2431 offer several flexible modes of
operation (internal or external SCK and free-running
conversion modes). These various modes do not require
programming configuration registers; moreover, they do
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2430/LTC2431 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2430/
LTC2431 achieve a minimum of 110dB rejection at the line
frequency (50Hz or 60Hz ±2%).
Ease of Use
The LTC2430/LTC2431 data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog inputs is easy.
The LTC2430/LTC2431 perform offset and full-scale cali-
brations in every conversion cycle. This calibration is trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.
24301f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC2430.PDF ] | |
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