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PDF PI74ALVCH16721 Data sheet ( Hoja de datos )
| Número de pieza | PI74ALVCH16721 | |
| Descripción | 3.3V 20-Bit Flip-Flop | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI74ALVCH16721
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3.3V 20-Bit Flip-Flop
with 3-STATE Outputs
Product Features
• PI74ALVCH16721 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced in the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16721 is a 20-bit flip-flop with 3-state outputs
designed specifically for 2.3V to 3.6V VCC operation. The
PI74ALVCH16721 is designed with edge-triggered D-type flip-
flops with qualified clock storage. On the positive transition of
clock (CLK) input, the device provides true data at the Q outputs,
provided that the clock-enable (CLKEN) input is LOW. If CLKEN
is HIGH, no data is stored.
A buffered output-enable (OE) input can be used to place the
20 outputs in either a normal logic state (HIGH or LOW level) or
a high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capacity to drive bus lines
without the need for interface or pullup components. OE does not
affect the internal operation of the flip-flops. Old data can be
retained or new data can be entered while the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH16721 data has Bus Hold which retains the
data inputs last state whenever the data input goes to high-
impedance preventing floating inputs and eliminating the need
for pullup/down resistors.
1
56
29
2
55
1 PS8090C 02/07/00
1 page  
PI74ALVCH16721
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Switching Characteristics over Operating Range(1)
Parameters
Description
Conditions(1) VCC = 2.5V ±0.2V
Min.(2) Max.
fCLOCK
fMAX
tPLH, tPHL
Clock Frequency
Maximum Frequency
Propogation Delay
CLK to Qx
0 150
150
5.6
tPZH, tPZL
Output Enable Time
OE to Qx
1.0 6.1
tPHX
tSU
tSU
tH
tH
tW
∆t/∆v(4)
Output Disable Time
OE to Qx
Data Before CLK↑
CL = 50pF
RL = 500Ω
CLKEN Before CLK↑
Data After CLK↑
CLKEN After CLK↑
Pulse Width(3)
CLK HIGH or LOW
Input Transition RISE or FALL
4
3.4
0
0
3.3
0
5.5
10
VCC = 2.7V
Min.(2) Max.
0 150
150
VCC = 3.3V ±0.3V
Min.(2) Max.
0 150
150
Units
MHz
5.1 4.3
1.0 5.8 1.0 4.8
4.7 4.4
3.6 3.1 ns
3.1 2.7
00
00
3.3 3.3
0 10 0 10 ns/V
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Recommended operating condition.
Operating Characteristics, TA = 25ºC
Parameter
CPD Power Dissipation
Capacitance
Outputs Enabled
Outputs Disabled
Test Conditions
CL = 50pF, f = 10 MHz
VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V
Typ.
55 59
46 49
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5 PS8090C 02/07/00
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| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PI74ALVCH16721.PDF ] | |
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