PDF CY7C1338 Data sheet ( Hoja de datos )

Número de pieza	CY7C1338
Descripción	128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CY7C1338 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns (117-MHz version) • Two-bit wraparound counter supporting either inter- leaved or linear burst sequence • Separate processor and controller address strobes pro- vide direct interface with the processor and external cache controller • Synchronous self-timed write • Asynchronous output enable • 3.3V I/Os • JEDEC-standard pinout • 100-pin TQFP packaging • ZZ “sleep” mode The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access. The CY7C1338 allows both interleaved and linear burst se- quences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. A synchronous self-timed write mechanism is provided to sim- plify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control. Logic Block Diagram CLK ADV ADSC ADSP A[16:0] GW BWE BW 3 BW 2 17 BW 1 BW 0 CE1 CE2 CE3 MODE (A0,A1) 2 BURST Q0 CE COUNTER CLR Q1 Q ADDRESS CE D REGISTER 15 D DQ[31:24] Q BYTEWRITE REGISTERS D DQ[23:16] Q BYTEWRITE REGISTERS D DQ[15:8] Q BYTEWRITE REGISTERS D DQ[7:0] Q BYTEWRITE REGISTERS D CE ENABLE REGISTER Q CLK 15 17 128K X 32 MEMORY ARRAY 32 32 OE ZZ SLEEP CONTROL INPUT REGISTERS CLK DQ[31:0] Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Intel and Pentium are registered trademarks of Intel Corporation. 7C1338-117 7.5 350 2.0 7C1338-100 8.0 325 2.0 7C1338-90 8.5 300 2.0 7C1338-50 11.0 250 2.0 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 5, 2000 1 page CY7C1338 Table 1. Counter Implementation for the Intel® Pentium®/80486 Processor’s Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 00 11 10 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 10 01 00 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Ac- cesses pending when entering the “sleep” mode are not con- sidered valid nor is the completion of the operation guaran- teed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Leaving ZZ unconnected defaults the device into an ac- tive state. Table 2. Counter Implementation for a Linear Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 10 11 00 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions ICCZZ Snooze mode standby current ZZ > VDD − 0.2V tZZS Device operation to ZZ > VDD − 0.2V ZZ tZZREC ZZ recovery time ZZ < 0.2V Min. 2tCYC Max. 10 2tCYC Unit mA ns ns 5 5 Page Timing Diagrams (continued) Read Cycle Timing[13, 15] CY7C1338 CLK Single Read tCYC tCH Burst Read Unselected Pipelined Read tADS ADSP tADH tCL tADS ADSC ADV tADVS tADH tAS tADVH ADD RD1 RD2 tAH GW tWS tWH WE CE1 tCES tCEH ADSP ignored with CE1 inactive ADSC initiated read Suspend Burst RD3 tWS tWH CE1 masks ADSP CE2 tCES CE3 tCES OE Data Out Unselected with CE2 tCEH tCEH tEOV tOEHZ tCDV 11aa tCLZ tDOH 2a 2b = DON’T CARE 2c 2c 2d = UNDEFINED 3a tCHZ Note: 15. RDx stands for Read Data from Address X. 11 11 Page

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