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PDF PHD36N03LT Data sheet ( Hoja de datos )
| Número de pieza | PHD36N03LT | |
| Descripción | N-channel TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
Rev. 02 — 8 June 2006
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
I Logic level compatible
I Low gate charge
1.3 Applications
I DC-to-DC converters
I Switched-mode power supplies
1.4 Quick reference data
I VDS ≤ 30 V
I RDSon ≤ 17 mΩ
I ID ≤ 43.4 A
I Ptot ≤ 57.6 W
2. Pinning information
Table 1. Pinning
Pin Description
1 gate (G)
2 drain (D)
3 source (S)
mb mounting base;
connected to drain
Simplified outline
[1]
mb
2
13
Symbol
mb
D
G
mbb076 S
SOT428 (DPAK)
123
SOT78 (3-lead TO-220AB)
[1] It is not possible to make a connection to pin 2 of the SOT428 package.
1 page  
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5. Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Static characteristics
V(BR)DSS drain-source breakdown
voltage
VGS(th) gate-source threshold voltage
IDSS drain leakage current
IGSS
RDSon
gate leakage current
drain-source on-state
resistance
Dynamic characteristics
QG(tot) total gate charge
QGS gate-source charge
QGD
gate-drain charge
Ciss input capacitance
Coss output capacitance
Crss reverse transfer capacitance
td(on)
turn-on delay time
tr rise time
td(off)
turn-off delay time
tf fall time
Source-drain diode
VSD source-drain voltage
Conditions
ID = 250 µA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
ID = 250 µA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 24 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±20 V; VDS = 0 V
VGS = 4.5 V; ID = 12 A; see Figure 6 and 8
Tj = 25 °C
Tj = 175 °C
VGS = 10 V; ID = 25 A; see Figure 6 and 8
VGS = 3.5 V; ID = 5.2 A; see Figure 6 and 8
ID = 36 A; VDS = 15 V; VGS = 10 V;
see Figure 11 and 12
VGS = 0 V; VDS = 25 V; f = 1 MHz;
see Figure 14
VDS = 15 V; RL = 0.6 Ω; VGS = 10 V;
RG = 10 Ω
IS = 25 A; VGS = 0 V; see Figure 13
Min Typ Max Unit
30 - - V
27 - - V
1 1.5 2 V
0.5 - - V
- - 2.2 V
-
0.05 1
µA
- - 500 µA
- 10 100 nA
- 18 22 mΩ
- 32.4 39.6 mΩ
- 14 17 mΩ
- 22 40 mΩ
- 18.5 - nC
- 4.2 - nC
- 2.9 - nC
- 690 - pF
- 160 - pF
- 110 - pF
- 6 - ns
- 10 - ns
- 33 - ns
- 19 - ns
- 0.97 1.2 V
PHD_PHP36N03LT_2
Product data sheet
Rev. 02 — 8 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 13
5 Page 
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 6. Revision history
Document ID
PHD_PHP36N03LT_2
Modifications:
PHD36N03LT-01
(9397 750 11613)
Release date
Data sheet status Change notice
Supersedes
20060608
Product data sheet -
PHD36N03LT-01
• The format of this data sheet has been redesigned to comply with the new presentation
and information standard of Philips Semiconductors.
• Addition of PHP36N03LT
20030630
Product data
-
-
PHD_PHP36N03LT_2
Product data sheet
Rev. 02 — 8 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
11 of 13
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