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PDF HY5V22FP Data sheet ( Hoja de datos )
| Número de pieza | HY5V22FP | |
| Descripción | 4 Banks x 1M x 32Bit Synchronous DRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No.
History
0.1 Defined Preliminary Specification
1) Modified FBGA Ball Configuration Typo.
2) Changed Functional Block Diagram from A10 to A11.
0.2
3) Changed VDD min from 3.0V to 3.135V.
4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.
5) Insert tAC2 Value.
6) Insdrt tRAS & CLK Value.
0.3 Defined IDD Spec.
0.4 Delited Preliminary.
0.5 Changed IDD Spec.
0.6 133MHz Speed Added
0.7 Changed FBGA Package Size from 11x13 to 8x13.
0.8
1) Changed VDD min from 3.135V to 3.0V.
2) Changed VIL min from VSSQ-0.3V to -0.3V.
0.9
Modified of size erra. (Page15)
(Equation : 13.00 ± 10 -> 13.00 ± 0.10)
Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / July 2004
1 page  
HY57V283220(L)T(P) / HY5V22(L)F(P)
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
Row Active
Row
Pre
Decoder
Column
Active
Column
Pre
Decoder
1M x32 Bank 3
1M x32 Bank 2
1M x32 Bank 1
1M x32 Bank 0
Memory
Cell
Array
Y decoder
DQ0
DQ1
DQ30
DQ31
Bank Select
Column Add
Counter
A0 Address
A1 Register
Burst
Counter
A11
BA0
BA1
Mode Register
CAS Latency
Data Out Control Pipe Line Control
Rev. 0.9 / July 2004
5
5 Page 
HY57V283220(L)T(P) / HY5V22(L)F(P)
DEVICE OPERATING OPTION TABLE
HY5xxxxxxxxx(P)-5
200MHz(5ns)
183MHz(5.5ns)
166MHz(6ns)
CAS Latency
3CLKs
3CLKs
3CLKs
HY5xxxxxxxxx(P)-55
tRCD
3CLKs
3CLKs
3CLKs
tRAS
8CLKs
8CLKs
7CLKs
tRC
11CLKs
10CLKs
10CLKs
tRP
3CLKs
3CLKs
3CLKs
tAC
4.5ns
5ns
5.5ns
tOH
1.5ns
2ns
2ns
183MHz(5.5ns)
166MHz(6ns)
143MHz(7ns)
CAS Latency
3CLKs
3CLKs
3CLKs
HY5xxxxxxxxx(P)-6
tRCD
3CLKs
3CLKs
3CLKs
tRAS
7CLKs
7CLKs
6CLKs
tRC
10CLKs
10CLKs
9CLKs
tRP
3CLKs
3CLKs
3CLKs
tAC
5ns
5.5ns
5.5ns
tOH
2ns
2ns
2ns
166MHz(6ns)
143MHz(7ns)
125MHz(8ns)
CAS Latency
3CLKs
3CLKs
3CLKs
HY5xxxxxxxxx(P)-7
tRCD
3CLKs
3CLKs
3CLKs
tRAS
7CLKs
6CLKs
6CLKs
tRC
10CLKs
9CLKs
9CLKs
tRP
3CLKs
3CLKs
3CLKs
tAC
5.5ns
5.5ns
6ns
tOH
2ns
2ns
2.5ns
143MHz(7ns)
125MHz(8ns)
100MHz(10ns)
CAS Latency
3CLKs
3CLKs
2CLKs
HY5xxxxxxxxx(P)-H
tRCD
3CLKs
3CLKs
2CLKs
tRAS
6CLKs
6CLKs
5CLKs
tRC
9CLKs
9CLKs
7CLKs
tRP
3CLKs
3CLKs
2CLKs
tAC
5.5ns
6ns
6ns
tOH
2ns
2ns
2ns
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
CAS Latency
3CLKs
3CLKs
2CLKs
HY5xxxxxxxxx(P)-8
tRCD
3CLKs
3CLKs
2CLKs
tRAS
6CLKs
6CLKs
5CLKs
tRC
9CLKs
9CLKs
7CLKs
tRP
3CLKs
3CLKs
2CLKs
tAC
5.5ns
6ns
6ns
tOH
2ns
2ns
2ns
125MHz(8ns)
100MHz(10ns)
83MHz(12ns)
CAS Latency
3CLKs
2CLKs
2CLKs
tRCD
3CLKs
2CLKs
2CLKs
tRAS
6CLKs
5CLKs
4CLKs
tRC
9CLKs
7CLKs
6CLKs
tRP
3CLKs
2CLKs
2CLKs
tAC
6ns
6ns
6ns
tOH
2ns
2ns
2.5ns
Rev. 0.9 / July 2004
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HY5V22FP.PDF ] | |
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