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PDF IDT72V71660 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V71660 | |
| Descripción | 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH | |
| Fabricantes | IDT | |
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3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
16,384 X 16,384
IDT72V71660
FEATURES:
• 16K x 16K non-blocking switching at 16.384Mb/s
• 64 serial input and output streams
• Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or
16.384Mb/s
• Per-channel Variable Delay Mode for low-latency applications
• Per-channel Constant Delay Mode for frame integrity applications
• Automatic identification of ST-BUS® and GCI bus interfaces
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high-impedance output control
• Direct microprocessor access to all internal memories
• Memory block programming for quick setup
• IEEE-1149.1 (JTAG) Test Port
• 3.3V Power Supply
• Available in 208-pin (17mm x 17mm) Plastic Ball Grid Array
(PBGA) and 208-pin (28mm x 28mm) Plastic Quad Flatpack
(PQFP) packages
• Operating Temperature Range -40°C to +85°C
DESCRIPTION:
The IDT72V71660 has a non-blocking switch capacity of 2,048 x 2,048
channels at 2.048Mb/s, 4,096 x 4,096 channels at 4.096Mb/s, and 8,192 x
8,192 channels at 8.192Mb/s and 16,384 x 16,384 channels at 16.384Mb/s.
With 64 inputs and 64 outputs, programmable per stream control, and a variety
of operating modes the IDT72V71660 is designed for the TDM time slot
interchange function in either voice or data applications.
Some of the main features of the IDT72V71660 are LOW power 3.3 Volt
operation, automatic ST-BUS® /GCI sensing, memory block programming,
simple microprocessor interface, one cycle direct internal memory accesses,
JTAG Test Access Port (TAP) and per stream programmable input offset delay,
variable or constant throughput modes, output enable and processor mode.
The IDT72V71660 is capable of switching up to 16,384 x 16,384 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per-channel basis.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
RESET
ODE
RX0
RX1
Receive
Serial Data
Streams
RX63
Timing Unit
Data Memory
MUX
TX0
TX1
Internal
Registers
Connection
Memory
Microprocessor Interface
Transmit
Serial Data
Streams
TX3
T1X32/OEI0
TX33/OEI1
JTAG Port
TX63/OEI31
CLK FP FE/HCLK WFPS
DS CS R/W A0-A15
DTA D0-D15
TMS TDI TCK TDO TRST
5905 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUSis a trademark of Mitel Corp.
1
2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
JUNE 2004
DSC-5905/10
1 page  
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
DESCRIPTION (CONTINUED)
The 64 serial input streams (RX) of the IDT72V71660 can run up to
16.384Mb/s allowing 256 channels per 125µs frame. The data rates on the
output streams (TX) are identical to those on the input streams (RX).
With two main operating modes, Processor Mode and Connection Mode, the
IDT72V71660 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor via Connection Memory. As
controlandstatusinformationiscriticalindatatransmission,theProcessorMode
is especially useful when there are multiple devices sharing the input and output
streams.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V71660
has a Frame Evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +7.5 clock cycles.
The IDT72V71660 also provides a JTAG Test Access Port, memory block
programming, a simple microprocessor interface and automatic ST-BUS® /GCI
sensing to shorten setup time, aid in debugging and ease use of the device
without sacrificing capabilities.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (FP) is used to mark the 125µs frame boundaries and to sequentially
address the input channels in Data Memory.
Data output on the TX streams may come from either the serial input streams
(Data Memory) or from the microprocessor (Connection Memory). In the case
that RX input data is to be output, the addresses in Connection Memory are used
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particular stream. In that way, more than one channel can output the same data.
In Processor Mode, the microprocessor writes data to the Connection Memory
locations corresponding to the stream and channel that is to be output. The lower
half (8 least significant bits) of the Connection Memory is output every frame until
the microprocessor changes the data or mode of the channel. By using this
Processor Mode capability, the microprocessor can access input and output
time-slots on a per-channel basis.
The two most significant bits of the Connection Memory are used to control
theper-channel modeoftheoutputstreams.Specifically,theMOD1-0bitsare
used to select Processor Mode, Constant or Variable delay Mode, and the high-
impedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly,
only that particular output channel (8 bits) will be in the high-impedance state.
If however, the ODE input pin is LOW and the Output Standby Bit in the Control
Register is LOW, all of the outputs will be in a high-impedance state even if a
particular channel in Connection Memory has enabled the output for that
channel. In other words, the ODE pin and Output Stand By control bit are master
output enables for the device (See Table 3).
SERIAL DATA INTERFACE TIMING
When a 16.384Mb/s serial data rate is required, the master clock frequency
will be running at 16.384 MHz resulting in a single-bit per clock. For all other
cases, 2.048Mb/s, 4.096Mb/s, and 8.192Mb/s, the master clock frequency will
be twice the data rate on the serial streams, resulting in two clocks per bit. Use
Table 5 to determine clock speed and the DR1-0 bits in the Control Register to
setup the device. The IDT72V71660 provides two different interface timing
modes, ST-BUS® or GCI. The IDT72V71660 automatically detects the pres-
ence of an input frame pulse and identifies it as either ST-BUS® or GCI.
InST-BUS®, whenrunningat16.384MHz,dataisclockedoutonthefalling
edge and is clocked in on the subsequent rising-edge. At all other data rates,
there are two clock cycles per bit and every second falling edge of the master
clock marks a bit boundary and the data is clocked in on the rising edge of CLK,
three quarters of the way into the bit cell. See Figure 14 for timing.
In GCI format, when running at 16.384 MHz, data is clocked out on the rising
edge and is clocked in on the subsequent falling edge. At all other data rates,
there are two clock cycles per bit and every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell. See Figure 15 for timing.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment.Although
all input data comes in at the same speed, delays can be caused by variable
path serial backplanes and variable path lengths which may be implemented
in large centralized and distributed switching systems. Because data is often
delayed, this feature is useful in compensating for the skew between input
streams.
Each input stream can have its own delay offset value by programming the
frameinputoffsetregisters(FOR,Table8).Themaximumallowableskewis+7.5
master clock (CLK) periods forward with a resolution of ½ clock period, see
Table 9. The output frame cannot be adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V71660 provides the Frame Evaluation input to determine
different data input delays with respect to the frame pulse FP. A measurement
cycle is started by setting the Start Frame Evaluation bit of the Control Register
LOW for at least one frame. When the Start Frame Evaluation bit in the Control
Register is changed from LOW to HIGH, the evaluation starts. Two frames later,
the Complete Frame Evaluation bit of the Frame Alignment Register changes
from LOW to HIGH to signal that a valid offset measurement is ready to be read
from bits 0 to 11 of the Frame Alignment Register. The Start Frame Evaluation
bit must be set to zero before a new measurement cycle is started.
In ST-BUS ® mode, the falling edge of the frame measurement signal (Frame
Evaluation) is evaluated against the falling edge of the ST-BUS® frame pulse.
In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising
edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of
the Frame Alignment Register.
MEMORY BLOCK PROGRAMMING
The IDT72V71660 provides users with the capability of initializing the entire
Connection Memory block in two frames. To set bits 14 and 15 of every
Connection Memory location, first program the desired pattern in the Block
Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register.
The block programming mode is enabled by setting the Memory Block
Program bit of the Control Register HIGH. When the Block Programming Enable
bit of the Control Register is set to HIGH, the Block Programming Data will be
loaded into the bits 14 and 15 of every Connection Memory location. The other
Connection Memory bits (bit 0 to bit 13) are loaded with zeros. When the memory
block programming is complete, the device resets the Block Programming
Enable , BPD 1-0 and MBP bits to zero.
5
5 Page 
IDT72V71660 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
INDUSTRIAL TEMPERATURERANGE
TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS
Reset Value:0000H for all FOR registers.
Register
15 14 13 12 11 10
9
8
7
65
43
2
10
FOR0Register OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
FOR1Register OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
FOR2Register OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8
FOR3Register OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR4Register OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170 DLE17 OD162 OD161 OF160 DLE16
FOR5Register OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210 DLE21 OF202 OF201 OF200 DLE20
FOR6Register OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250 DLE25 OF242 OF241 OF240 DLE24
FOR7Register OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290 DLE29 OF282 OF281 OF280 DLE28
FOR8Register OF352 OF351 OF350 DLE35 OF342 OF341 OF340 DLE34 OF332 OF331 OF330 DLE33 OF322 OF321 OF320 DLE32
FOR9Register OF392 OF391 OF390 DLE39 OF382 OF381 OF380 DLE38 OF372 OF371 OF370 DLE37 OF362 OF361 OF360 DLE36
FOR10Register OF432 OF431 OF430 DLE43 OF422 OF421 OF420 DLE42 OF412 OF411 OF410 DLE41 OF402 OF401 OF400 DLE40
FOR11Register OF472 OF471 OF470 DLE47 OF462 OF461 OF460 DLE46 OF452 OF451 OF450 DLE45 OF442 OF441 OF440 DLE44
FOR12Register OF512 OF511 OF510 DLE51 OF502 OF501 OF500 DLE50 OF492 OF491 OF490 DLE49 OF482 OF481 OF480 DLE48
FOR13Register OF552 OF551 OF550 DLE55 OF542 OF541 OF540 DLE54 OF532 OF531 OF530 DLE53 OF522 OF521 OF520 DLE52
FOR14Register OF592 OF591 OF590 DLE59 OF582 OF581 OF580 DLE58 OF572 OF571 OF570 DLE57 OF562 OF561 OF560 DLE56
FOR15Register OF632 OF631 OF630 DLE63 OF622 OF621 OF620 DLE62 OF612 OF611 OF610 DLE61 OF602 OF601 OF600 DLE60
Name(1)
Description
OFn2, OFn1, OFn0
(Offset Bits 2, 1 & 0)
These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame.
The input frame offset can be selected to +7.5 clock periods from the point where the external frame pulse input signal is applied to the FP
input of the device. See Figure 2.
DLEn
ST-BUS® and
GCI mode:
DLEn = 0, offset is on the clock boundary
DLEn = 1, offset is a half clock cycle off of the clock boundary.
NOTE:
1. n denotes an input stream number from 0 to 63.
11
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| PDF Descargar | [ Datasheet IDT72V71660.PDF ] | |
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