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PDF CY2DP3110 Data sheet ( Hoja de datos )
| Número de pieza | CY2DP3110 | |
| Descripción | Differential Clock/Data Fanout Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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FastEdge™ Series
CY2DP3110
1 of 2:10 Differential Clock/Data Fanout Buffer
Features
• Ten ECL/PECL differential outputs
• One ECL/PECL differential or single-ended inputs
(CLKA)
• One HSTL differential or single-ended inputs (CLKB)
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 400 ps propagation delay (typical)
• 1.2 ps RMS period jitter (max.)
• 1.5 GHz Operation (2.7 GHz maximum toggle
frequency)
• PECL and HSTL mode supply range: VCC = 2.5V± 5% to
3.3V±5% with VEE = 0V
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%
with VCC = 0V
• Industrial temperature range: –40°C to 85°C
• 32-pin TQFP package
• Temperature compensation like 100K ECL
• Pin-compatible with MC100ES6111
Functional Description
The CY2DP3110 is a low-skew, low propagation delay 2-to-10
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths that are multi-
plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP3110 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on HSTL
single-ended signal to 10 ECL/PECL differential loads. An ex-
ternal bias pin, VBB, is provided for this purpose. In such an
application, the VBB pin should be connected to either one of
the CLKA# or CLKB# inputs and bypassed to ground via a
0.01-µF capacitor. Traditionally, in ECL, it is used to provide
the reference level to a receiving single-ended input that might
have a different self-bias point.
Since the CY2DP3110 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in com-
munication systems. Furthermore, advanced circuit design
schemes, such as internal temperature compensation, ensure
that the CY2DP3110 delivers consistent performance over
various platforms
Block Diagram
VCC
CLKA
CLKA#
VEE
VCC
CLKB
CLKB#
CLK_SEL
VEE
VEE
VBB
VBB
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
Pin Configuration
VCC 1
24 Q3
CLK_SEL 2
23 Q3#
CLKA 3
22 Q4
CLKA#
VBB
4
5
CY2DP3110
21
20
Q4#
Q5
CLKB 6
19 Q5#
CLKB# 7
18 Q6
VEE 8
17 Q6#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07469 Rev.*G
Revised July 28, 2004
1 page  
FastEdge™ Series
CY2DP3110
Timing Definitions
VCC
V IH
VCMR Max = VCC
VPP
VPP range
0.1V - 1.3V
VCM R
V IL
VCM R M in = VEE + 1.2
VEE
VCC
V IH
Figure 1. PECL/ECL Input Waveform Definitions
V C C = 3 .3 V
V X m a x = 0 .9 V
V D IF
V D IF = > =
0 .4 V m in
VX
V IL
VEE
V E E = 0 .0 V
V X M in = 0 .6 8
Figure 2. HSTL Differential Input Waveform Definitions
tr, tf,
20-80%
VO
Figure 3. ECL/LVPECL Output
In p u t
C lo c k
TPLH,
TPD
O u tp u t
C lo c k
TPHL
A n o th e r
O u tp u t
C lo c k
VPP
VO
tS K (O )
Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O))
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
Document #: 38-07469 Rev.*G
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY2DP3110.PDF ] | |
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