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HY62UF16800B の電気的特性と機能

HY62UF16800BのメーカーはHynix Semiconductorです、この部品の機能は「512Kx16bit full CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 HY62UF16800B
部品説明 512Kx16bit full CMOS SRAM
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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HY62UF16800B Datasheet, HY62UF16800B PDF,ピン配置, 機能
www.DataSheet4U.com
Document Title
512K x16 bit 3.0V Super Low Power Full CMOS slow SRAM
Revision History
Revision No History
00 Initial Release
01 DC Para Change
Icc 4mA à 3mA
Icc1(Min) 40mA à 20mA
Icc1(1us) 8mA à 2mA
Isb 0.1mA à 0.3mA
Isb1 25uA à 15uA
Iccdr
12uA à 6uA
02 Pin Connection
E3 DNU à E3 NC
HY62UF16800B Series
512Kx16bit full CMOS SRAM
Draft Date
Remark
May.29.2001 Preliminary
Mar.20.2002
Apr.10.2002
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 / Apr. 2002
Hynix Semiconductor

1 Page





HY62UF16800B pdf, ピン配列
ORDERING INFORMATION
Part No.
Speed
HY62UF16800B-DFC 55/70/85
HY62UF16800B-DFI
55/70/85
Note 1. C : Commercial, I : Industrial
Power
LL-part
LL-part
Package
FBGA
FBGA
Temp.
C
I
HY62UF16800B
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
TA
TSTG
PD
TSOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.3 to Vcc+0.3
-0.3 to 4.6
0 to 70
-40 to 85
-55 to 150
1.0
260 10
Unit
V
V
°C
°C
°C
W
°C sec
Remark
HY62UF16800B-C
HY62UF16800B-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1 CS2 /WE /OE /LB /UB Mode
I/O Pin
I/O1~I/O8 I/O9~I/O16
H X X X XX
Hi-Z Hi-Z
X L X X X X Deselected
Hi-Z
Hi-Z
X X X X HH
Hi-Z Hi-Z
L
L
H
H
H
H
H
H
L
X
X
L
Output Disabled
Hi-Z
Hi-Z
Hi-Z
Hi-Z
L H H L LH
DOUT
Hi-Z
HL
Read
Hi-Z
DOUT
LL
DOUT
DOUT
L H L X LH
DIN Hi-Z
HL
Write
Hi-Z
DIN
LL
DIN DIN
Note:
1. H=VIH, L=VIL, X=don't care(VIH or VIL)
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When /UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Power
Standby
Active
Active
Active
Rev.02/Apr. 2002
2


3Pages


HY62UF16800B 電子部品, 半導体
HY62UF16800B
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
ADDR
/CS1
tAA
tACS
tRC
tOH
CS2
/UB ,/ LB
tBA
/OE
Data
Out
High-Z
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
READ CYCLE 2(Note 1,2,4)
ADDR
Data
Out
tAA
tOH
Previous Data
READ CYCLE 3(Note 1,2,4)
tRC
tCHZ(3)
tBHZ(3)
tOHZ(3)
Data Valid
Data Valid
tOH
/CS1
/UB, /LB
CS2
Data
Out
tACS
tCLZ(3)
Data Valid
tCHZ(3)
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and
CS2 are in active status.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
Rev.02/Apr. 2002
5

6 Page



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部品番号部品説明メーカ
HY62UF16800B

512Kx16bit full CMOS SRAM

Hynix Semiconductor
Hynix Semiconductor


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