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HY62LF16804B の電気的特性と機能

HY62LF16804BのメーカーはHynix Semiconductorです、この部品の機能は「512Kx16bit full CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 HY62LF16804B
部品説明 512Kx16bit full CMOS SRAM
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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HY62LF16804B Datasheet, HY62LF16804B PDF,ピン配置, 機能
www.DataSheet4U.com
Document Title
512K x16 bit 2.5V Super Low Power Full CMOS slow SRAM
Revision History
Revision No History
00 Initial Release
HY62LF16804B Series
512Kx16bit full CMOS SRAM
Draft Date
Remark
May.29.2001 Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.00 /May.2001
Hynix Semiconductor

1 Page





HY62LF16804B pdf, ピン配列
ORDERING INFORMATION
Part No.
Speed
HY62LF16804B-DFC 70/85/100
HY62LF16804B-SFC 70/85/100
HY62LF16804B-DFI 70/85/100
HY62LF16804B-SFI 70/85/100
Note 1. C : Commercial, I : Industrial
Power
LL-part
SL-part
LL-part
SL-part
Package
fBGA
fBGA
fBGA
fBGA
Temp.
C
C
I
I
HY62LF16804B Series
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
TA
TSTG
PD
TSOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.3 to Vcc+0.3
-0.3 to 3.6
0 to 70
-40 to 85
-55 to 150
1.0
260 10
Unit
V
V
°C
°C
°C
W
°C sec
Remark
HY62LF16804B-C
HY62LF16804B-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS /WE /OE /LB /UB
Mode
I/O
I/O1~I/O8 I/O9~I/O16
Power
H X X X X Deselected
High-Z
High-Z
Standby
X X X H H Deselected
High-Z
High-Z
Standby
L H H L X Output Disabled High-Z
High-Z
Active
L H H X L Output Disabled High-Z
High-Z
Active
L H L L H Read
DOUT
High-Z
Active
HL
High-Z
DOUT
LL
DOUT
DOUT
L L X L H Write
DIN
High-Z
Active
HL
High-Z
DIN
LL
DIN DIN
Note:
1. H=VIH, L=VIL, X=don't care(VIH or VIL)
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.00/May. 2001
2


3Pages


HY62LF16804B 電子部品, 半導体
HY62LF16804B Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
ADDR
/CS
/UB ,/ LB
/OE
Data
Out
High-Z
tAA
tACS
tRC
tBA
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
tOH
tCHZ(3)
tBHZ(3)
tOHZ(3)
Data Valid
READ CYCLE 2(Note 1,2,4)
ADDR
Data
Out
tAA
tOH
Previous Data
tRC
Data Valid
tOH
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
Data
Out
tACS
tCLZ(3)
Data Valid
tCHZ(3)
Notes:
1. Read occurs during the overlap of a low /OE, a high /WE, a low /CS and low /UB and /or /LB
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.00/May. 2001
5

6 Page



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共有リンク

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部品番号部品説明メーカ
HY62LF16804A

512Kx16bit full CMOS SRAM

Hynix
Hynix
HY62LF16804B

512Kx16bit full CMOS SRAM

Hynix Semiconductor
Hynix Semiconductor


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