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HY29F400A の電気的特性と機能

HY29F400AのメーカーはHynix Semiconductorです、この部品の機能は「4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 HY29F400A
部品説明 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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HY29F400A Datasheet, HY29F400A PDF,ピン配置, 機能
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HY29F400A
4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
KEY FEATURES
5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
High Performance
– Access times as fast as 50 ns
Low Power Consumption
– 20 mA typical active read current in byte
mode, 28 mA typical in word mode
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current
Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
Sector Erase Architecture
– Boot sector architecture with top and
bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and seven 64 Kbyte sectors in byte mode
– One 8 Kword, two 4 Kword, one 16 Kword
and seven 32 Kword sectors in word mode
– A command can erase any combination of
sectors
– Supports full chip erase
Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F400A is a 4 Megabit, 5 volt only CMOS
Flash memory organized as 524,288 (512K) bytes
or 262,144 (256K) words. The device is offered in
industry-standard 44-pin PSOP and 48-pin TSOP
packages.
The HY29F400A can be programmed and erased
in-system with a single 5-volt VCC supply. Internally
generated and regulated voltages are provided for
program and erase operations, so that the device
does not require a high voltage power supply to
perform those functions. The device can also be
programmed in standard EPROM programmers.
Access times as fast as 55 ns over the full operat-
ing voltage range of 5.0 volts ± 10% are offered
for timing compatibility with the zero wait state re-
quirements of high speed microprocessors. A 55
ns version operating over 5.0 volts ± 5% is also
Preliminary
Revision 1.0, January 2002
Sector Protection
– Any combination of sectors may be locked
to prevent program or erase operations
within those sectors
Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 11 sec typical
Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
Ready/Busy# Output (RY/BY#)
– Provides hardware confirmation of
completion of program and erase
operations
100,000 Program/Erase Cycles Minimum
Space Efficient Packaging
– Available in industry-standard 44-pin
PSOP and 48-pin TSOP and reverse
TSOP packages
LOGIC DIAGRAM
18
A[17:0]
CE#
OE#
WE#
RESET#
BYTE#
DQ[7:0]
DQ[14:8]
DQ[15]/A-1
RY/BY#
8
7

1 Page





HY29F400A pdf, ピン配列
PIN CONFIGURATIONS
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RESET#
43 WE#
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
32 VSS
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard
TSOP48
HY29F400A
48 A16
47 BYTE#
46 VSS
45 DQ15/A-1
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 VSS
26 CE#
25 A0
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse
TSOP48
48 A15
47 A14
46 A13
45 A12
44 A11
43 A10
42 A9
41 A8
40 NC
39 NC
38 WE#
37 RESET#
36 NC
35 NC
34 RY/BY#
33 NC
32 A17
31 A7
30 A6
29 A5
28 A4
27 A3
26 A2
25 A1
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A #symbol following the
signal name, e.g., RESET#, indicates that the sig-
nal is asserted in a Low state (nominally 0 volts).
Rev. 1.0/Jan. 02
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, . . .
, E, F) indicates a number expressed in hexadeci-
mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
3


3Pages


HY29F400A 電子部品, 半導体
HY29F400A
Table 2. HY29F400A Normal Bus Operations 1
Operation
CE# OE# WE# RESET# Address 2
Read
L
Write
L
Output Disable
L
CE# TTL Standby
H
CE# CMOS Standby VCC ± 0.5V
Hardware Reset
(TTL Standby)
X
L
H
H
X
X
X
HH
LH
HH
XH
X VCC ± 0.5V
XL
AIN
AIN
X
X
X
X
DQ[7:0]
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
DQ[15:8] 3
BYTE# = H BYTE# = L
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z High-Z
Hardware Reset
(CMOS Standby)
X
X
X VSS ± 0.5V
X
High-Z High-Z
Notes:
1. L = VIL, H = VIH, X = Dont Care, DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.
2. Address is A[17:-1] in Byte Mode and A[17:0] in Word Mode.
3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
High-Z
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Read Operation
Data is read from the HY29F400A by using stan-
dard microprocessor read cycles while placing the
address of the byte or word to be read on the
devices address inputs, A[17:0] in Word mode
(BYTE# = H) or A[17:-1] in Byte mode (BYTE# =
L) . As shown in Table 2, the host system must
drive the CE# and OE# inputs Low and drive WE#
High for a valid read operation to take place. The
device outputs the specified array data on DQ[7:0]
in Byte mode and on DQ[15:0] in Word mode.
Note that DQ[15] serves as address input A[-1]
when the device is operating in Byte mode.
The HY29F400A is automatically set for reading
array data after device power-up and after a hard-
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host attempts to read from an
address within an erase-suspended sector, or
while the device is performing an erase or byte/
word program operation, the device outputs sta-
tus data instead of array data. After completing a
programming operation in the Erase Suspend
mode, the system may once again read array data
with the same exceptions noted above. After com-
pleting an internal program or internal erase algo-
rithm, the HY29F400A automatically returns to the
Read Array Data mode.
The host must issue a hardware reset or the soft-
ware reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the Read Array Data
mode while it is in the Electronic ID mode.
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F400A. Writes to the device are performed
by placing the byte or word address on the devices
address inputs while the data to be written is input
on DQ[7:0] in Byte mode (BYTE# = L) and on
DQ[15:0] in Word mode (BYTE# = H). The host
system must drive the CE# and WE# pins Low
and drive OE# High for a valid write operation to
take place. All addresses are latched on the fall-
ing edge of WE# or CE#, whichever happens later.
All data is latched on the rising edge of WE# or
CE#, whichever happens first.
6 Rev. 1.0/Jan. 02

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共有リンク

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HY29F400

4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory

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