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ADSP-BF544 の電気的特性と機能

ADSP-BF544のメーカーはAnalog Devicesです、この部品の機能は「(ADSP-BF54x) Embedded Processor」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADSP-BF544
部品説明 (ADSP-BF54x) Embedded Processor
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADSP-BF544 Datasheet, ADSP-BF544 PDF,ピン配置, 機能
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Preliminary Technical Data
Blackfin®
Embedded Processor
ADSP-BF542/BF544/BF548/BF549
FEATURES
Up to 600 MHz High-Performance Blackfin Processor
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs
RISC-Like Register and Instruction Model
0.8 V to TBD V Core VDD with On-chip Voltage Regulation
2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins
400-ball Lead-Free mBGA Package
MEMORY
Up to 324K bytes of on-chip memory comprised of:
Instruction SRAM/cache; instruction SRAM;
data SRAM/cache; additional dedicated data SRAM;
scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations
External Sync Memory Controller Supporting
DDR/Mobile DDR SDRAM
External Async Memory Controller Supporting 8/16 bit Async
Memories and Burst Flash Devices
NAND Flash Controller
Four Memory-to-Memory DMA pairs, two with external
requests
Memory Management Unit Providing Memory Protection
Flexible Booting Options
Code Security with LockboxTM Secure Technology
One-Time-Programmable (OTP) Memory
PERIPHERALS
High-Speed USB On-the-Go (OTG) with Integrated PHY
SD/SDIO Controller
ATA/ATAPI-6 Controller
Up to Four Synchronous Serial Ports (SPORTs)
Up to Three Serial Peripheral Interfaces (SPI-Compatible)
Up to Four UARTs, Two with Automatic Hardware Flow
Control
Up to Two CAN (Controller Area Network) 2.0B Interfaces
Up to Two TWI (Two-Wire Interface) Controllers
8- or 16-Bit Asynchronous Host DMA Interface
Multiple Enhanced Parallel Peripheral Interfaces (PPI), Sup-
porting ITU-R BT.656 Video Formats and 18/24-bit LCD
Connections
Media Transceiver (MXVR) for connection to a MOST®
Network
Pixel Compositor for overlays, alpha blending, and color
conversion
Up to Eleven 32-Bit Timers/Counters with PWM Support
Real-Time Clock (RTC) and Watchdog Timer
Up/Down Counter With Support for Rotary Encoder
Up to 152 General Purpose I/O (GPIOs)
On-Chip PLL Capable of 1x to 63x Frequency Multiplication
Debug/JTAG Interface
CAN (0-1)
TWI (0-1)
TIMERS(0-10)
COUNTER
KEYPAD
PAB 16
VOLTAGE
REGULATOR
JTAG TEST AND
EMULATION
RTC
B
WATCHDOG
TIMER
OTP
INTERRUPTS
L2
SRAM
L1
INSTR ROM
L1
INSTR SRAM
L1
DATA SRAM
HOST
UART (0-1)
UART (2-3)
SPI (0-1)
MXVR
USB
DCB 32
BOOT
ROM
EAB 64
DEB 32
EXTERNAL PORT
NOR, DDR1 CONTROL
DDR1
16
ASYNC
16
32-BIT DMA
16-BIT DMA
DAB32 32
DAB16 16
ATAPI
NAND FLASH
CONTROLLER
SPI (2)
SPORT (2-3)
SPORT (0-1)
SD / SDIO
EPPI (0-2)
PIXEL
C OM PO SITOR
Figure 1. Functional Block Diagram
• Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/461-3113 © 2006 Analog Devices, Inc. All rights reserved.

1 Page





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Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-BF54x processors are members of the Blackfin fam-
ily of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin processors combine a dual-
MAC state-of-the-art signal processing engine, the advantages
of a clean, orthogonal RISC-like microprocessor instruction set,
and single-instruction, multiple-data (SIMD) multimedia capa-
bilities into a single instruction-set architecture.
Specific performance and memory configurations for
ADSP-BF54x processors are shown in Table 1.
Table 1. ADSP-BF54x Processor Features
Processor
Features
Code Security
1111
SD/SDIO
11–1
Pixel Compositor
1111
18- or 24-bit PPI0 with LCD
111–
16-bit PPI1, 8-bit PPI2
1111
Host DMA Port
111–
DDR/NAND Flash
1111
ATAPI
11–1
USB 2.0 HS OTG
11–1
Keyscan
11–1
MXVR
1–––
CAN ports
2221
TWI ports
2221
SPI ports
3322
UART ports
4433
SPORTs
4433
General-purpose counter
1111
Timers
8 8 11 8
General-purpose I/O pins
152 152 152 152
Memory
L1 Instruction SRAM/Cache 16 16 16 16
Configurations L1 Instruction SRAM
(K Bytes)
L1 Data SRAM/Cache
48 48 48 48
32 32 32 32
L1 Data SRAM
32 32 32 32
L1 Scratchpad SRAM
4444
L1 ROM1
64 64 64 64
L2 128 128 64 –
L3 Boot ROM1
4444
Maximum Core Instruction Rate (MHz)
533 600 533 600
1 This ROM is not customer configurable.
ADSP-BF54x
The ADSP-BF542/BF544/BF548 processors are completely code
and pin compatible. They differ only with respect to their per-
formance, on-chip memory, and selection of I/O peripherals.
Specific performance, memory, and feature configurations, are
shown in Table 1. The ADSP-BF549 is completely code compat-
ible with the other ADSP-BF54x processors, and this processor
is pin compatible, except for the location of the HWAIT pin.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support and leading-edge signal
processing in one integrated package.
LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature on-chip
dynamic power management, the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
substantial reduction in power consumption, compared with
just varying the frequency of operation. This translates into
longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF54x processors are highly integrated system-on-a-
chip solutions for the next generation of embedded network
connected applications. By combining industry-standard inter-
faces with a high performance signal processing core, users can
develop cost-effective solutions quickly without the need for
costly external components. The system peripherals include a
high speed USB OTG (On-The-Go) controller with integrated
PHY, CAN 2.0B controllers, TWI controllers, UART ports, SPI
ports, serial ports (SPORTs), ATAPI controller, SD/SDIO con-
troller, a real-time clock, a watchdog timer, LCD controller, and
multiple enhanced parallel peripheral interfaces.
ADSP-BF54X PROCESSOR PERIPHERALS
The ADSP-BF54x processor contains a rich set of peripherals
connected to the core via several high bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see Figure 1 on Page 1). The general-pur-
pose peripherals include functions such as UARTs, SPI, TWI,
timers with pulse width modulation (PWM) and pulse measure-
ment capability, general purpose I/O pins, a real-time clock, and
a watchdog timer. This set of functions satisfies a wide variety of
typical system support needs and is augmented by the system
expansion capabilities of the part. The ADSP-BF54x processor
contains dedicated network communication modules and high-
speed serial and parallel ports, an interrupt controller for flexi-
ble management of interrupts from the on-chip peripherals or
external sources, and power management control functions to
tailor the performance and power characteristics of the proces-
sor and system to many application scenarios.
Rev. PrD | Page 3 of 64 | November 2006


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ADSP-BF544 電子部品, 半導体
www.DataSheet4U.com
ADSP-BF54x
The memory DMA controllers (DMAC1 and DMAC0) pro-
vides high-bandwidth data-movement capability. They can
perform block transfers of code or data between the internal
memory and the external memory spaces.
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA2 4000
0xFFA1 4000
0xFFA1 0000
0xFFA0 C000
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xFEB2 0000
0xFEB0 0000
0xEF00 1000
0xEF00 0000
0x3000 0000
0x2C00 0000
0x2800 0000
0x2400 0000
0x2000 0000
TOP OF LAST
DDR PAGE
0x0000 0000
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
L1 ROM (64K BYTE)
INSTRUCTION SRAM / CACHE (16K BYTE)
RESERVED
INSTRUCTION BANK B SRAM (16K BYTE)
INSTRUCTION BANK A SRAM (32K BYTE)
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
DATA BANK B SRAM (16K BYTE)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTE)
DATA BANK A SRAM (16K BYTE)
RESERVED
L2 SRAM (128K BYTE)
RESERVED
BOOT ROM (4K BYTE)
RESERVED
ASYNC MEMORY BANK 3 (64M BYTE)
ASYNC MEMORY BANK 2 (64M BYTE)
ASYNC MEMORY BANK 1 (64M BYTE)
ASYNC MEMORY BANK 0 (64M BYTE)
RESERVED
DDR1 MEM BANK 1 (8M BYTE - 256M BYTE)
DDR1 MEM BANK 0 (8M BYTE - 256M BYTE)
Figure 3. ADSP-BF549 Internal/External Memory Map1
1 This memory map applies to all ADSP-BF54x processors, except for L2 memory
population. For details, see Table 1.
Internal (On-Chip) Memory
The ADSP-BF54x processor has several blocks of on-chip mem-
ory providing high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, and also 16K bytes that can be configured as a
four-way set-associative cache or SRAM. This memory is
accessed at full processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of 64K bytes SRAM, of which 32K bytes can be
configured as a two-way set associative cache. This memory
block is accessed at full processor speed.
Preliminary Technical Data
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
The fourth memory block is the factory programmed L1
instruction ROM, operating at full processor speed. This ROM
is not customer configurable.
The fifth memory block is the L2 SRAM, providing 128K bytes
of unified Instruction and data memory, operating at one half
the frequency of the core.
Finally, there is a 4K boot ROM that can be seen as L3 memory.
It operates at full SCLK rate.
External (Off-Chip) Memory
Through the External Bus Interface Unit (EBIU) the
ADSP-BF54x processors provide glueless connectivity to exter-
nal 16-bit wide memories, such as DDR SDRAM, Mobile DDR,
SRAM, NOR flash, NAND flash, and FIFO devices. To provide
the best performance, the bus system of the DDR interface is
completely separate from the other parallel interfaces.
The DDR memory controller can gluelessly manage up to two
banks of double-rate synchronous dynamic memory (DDR1
SDRAM). The 16-bit wide interface operates at SCLK frequency
enabling maximum throughput of 532 Mbyte/s. The DDR or
Mobile DDR controller is augmented with a queuing mecha-
nism that performs efficient bursts onto the DDR. The
controller is an industry standard DDR SDRAM controller with
each bank supporting from 64 Mbit to 512 Mbit device sizes and
4-, 8-, or 16-bit widths. The controller supports up to 512
Mbytes in one bank, but the total in two banks is limited to 512
Mbytes. Each bank is independently programmable and is con-
tiguous with adjacent banks regardless of the sizes of the
different banks or their placement.
Traditional 16-bit asynchronous memories, such as SRAM,
EPROM, and flash devices, can be connected to one of the four
64 MByte asynchronous memory banks, represented by four
memory select strobes. Alternatively, these strobes can function
as bank-specific read or write strobes preventing further glue
logic when connecting to asynchronous FIFO devices.
In addition, the external bus can connect to advanced flash
device technologies, such as:
• Page-mode NOR flash devices
• Synchronous burst-mode NOR flash devices
• NAND flash devices
NAND Flash Controller (NFC)
The ADSP-BF54x provides a NAND Flash Controller (NFC) as
part of the external bus interface. NAND flash devices provide
high-density, low-cost memory. However, NAND flash devices
also have long random access times, invalid blocks, and lower
reliability over device lifetimes. Because of this, NAND flash is
often used for read-only code storage. In this case, all DSP code
can be stored in NAND flash and then transferred to a faster
memory (such as DDR or SRAM) before execution. Another
common use of NAND flash is for storage of multimedia files or
other large data segments. In this case, a software file system
Rev. PrD | Page 6 of 64 | November 2006

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共有リンク

Link :


部品番号部品説明メーカ
ADSP-BF542

(ADSP-BF54x) Embedded Processor

Analog Devices
Analog Devices
ADSP-BF544

(ADSP-BF54x) Embedded Processor

Analog Devices
Analog Devices
ADSP-BF547

High Performance Convergent Multimedia Blackfin Processor

Analog Devices
Analog Devices
ADSP-BF548

(ADSP-BF54x) Embedded Processor

Analog Devices
Analog Devices


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