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IDT70T9169 の電気的特性と機能

IDT70T9169のメーカーはIDTです、この部品の機能は「(IDT70T9159L / IDT70T9169) HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IDT70T9169
部品説明 (IDT70T9159L / IDT70T9169) HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
メーカ IDT
ロゴ IDT ロゴ 




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IDT70T9169 Datasheet, IDT70T9169 PDF,ピン配置, 機能
www.DataSheet4U.com
HIGH-SPEED 2.5V
16/8K X 9 SYNCHRONOUS
PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70T9169/59L
.eatures
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial:7.5/9/12ns (max.)
– Industrial: 9ns (max.)
x Low-power operation
– IDT70T9169/59L
Active: 225mW (typ.)
Standby: 1.5mW (typ.)
x Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
.unctional Block Diagram
x Full synchronous operation on both ports
4.0ns setup to clock and 0.5ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 7.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
12ns cycle time, 83MHz operation in Pipelined output mode
x LVTTL- compatible, single 2.5V (±100mV) power supply
x Industrial temperature range (–40°C to +85°C) is
available for 66MHz
x Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
A13L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
NOTE:
1. A13 is a NC for IDT70T9159.
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O8R
A13R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5654 drw 01
©2002 Integrated Device Technology, Inc.
1
JULY 2002
DSC-5654/1

1 Page





IDT70T9169 pdf, ピン配列
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configurations (con't.)(1,2,3,4)
70T9169/59BF
BF100(5)
06/21/02
100-Pin fpBGA
Top View(6)
A1 A2
A3 A4
A5 A6 A7
A8 A9
A10
A6R A9R A12R NC VSS VSS NC R/WR VSS NC
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
A4R A5R A8R A10R NC NC NC OER NC I/O6R
C1 C2 C3 C4 C5 C6 C7 C8
C9 C10
A3R NC NC A7R NC CE0R CE1R PL/FTR I/O7R I/O3R
D1 D2 D3 D4 D5 D6 D7
D8 D9 D10
A0R CLKR A1R A2R A11R A13R(1) CNTRSTR I/O8R I/O5R I/O1R
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
VSS ADSR CNTENR A1L ADSL VSS I/O4R I/O2R I/O0R VDD
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
VSS CLKL A0L A3L VDD VSS VDD I/O2L I/O1L I/O0L
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10
CNTENL NC A5L A12L NC R/WL NC I/O4L VSS I/O3L
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
A2L A4L A9L A13L(1) NC CE1L NC I/O7L I/O6L I/O5L
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
NC A7L A10L NC NC NC OEL VSS VSS I/O8L
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
A6L A8L A11L NC VDD VDD CE0L CNTRSTL PL/FTL NC
,
NOTES:
1. A13 is a NC for IDT70T9159.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
5654 drw 03
6.342


3Pages


IDT70T9169 電子部品, 半導体
IDT70T9169/59L
High-Speed 2.5V 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VDD = 2.5V ± 100mV)
70T9169/59L
Symbol
Parameter
|ILI| Input Leakage Current(1)
|ILO| Output Leakage Current
VOL Output Low Voltage
Test Conditions
VDD = 2.6V, VIN = 0V to VDD
CE = VIH or CE1 = VIL, VOUT = 0V to VDD
IOL = +2mA
Min. Max. Unit
___ 5 µ A
___ 5 µ A
___ 0.4 V
VOH Output High Voltage
IOH = -2mA
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
2.0 ___ V
5654 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV)
70T9169/59L7
Com'l Only
70T9169/59L9
Com'l & Ind
70T9169/59L12
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(4)
Max. Typ.(4)
Max. Typ.(4)
Max. Unit
IDD Dynamic Operating CEL and CER= VIL,
Current (Both
Outputs Disabled,
Ports Active)
f = fMAX(1)
COM'L L 80 200 75 175 70 150 mA
IND L ____ ____ 75 220 ____ ____
ISB1 Standby Current CEL = CER = VIH
(Both Ports - TTL
Level Inputs)
f = fMAX(1)
COM'L L 20 60 20 50 20 40 mA
IND L ____ ____ 20 70 ____ ____
ISB2 Standby
Current (One
Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH(5)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L L 50
115 47 100 45
85 mA
IND L ____ ____ 47 190 ____ ____
ISB3 Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER >VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L L 0.1 3.0 0.1 3.0 0.1 3.0 mA
IND L ____ ____ 0.1 3.0 ____ ____
ISB4 Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L L 50
115 47 100 45
85 mA
CE"B" > VDD - 0.2V(5)
VIN > VDD - 0.2V or
IND L
VIN < 0.2V, Active Port,
____ ____ 47 190 ____ ____
Outputs Disabled, f = fMAX(1)
NOTES:
5654 tbl 09
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 2.5V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 75mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.642

6 Page



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部品番号部品説明メーカ
IDT70T9169

(IDT70T9159L / IDT70T9169) HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT
IDT


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