FM32256 の電気的特性と機能

FM32256のメーカーはRamtronです、この部品の機能は「(FM3204 - FM32256) Integrated Processor Companion」です。

製品の詳細 ( Datasheet PDF )

部品番号 FM32256
部品説明 (FM3204 - FM32256) Integrated Processor Companion
メーカ Ramtron
ロゴ Ramtron ロゴ 


Total 20 pages

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FM32256 Datasheet, FM32256 PDF,ピン配置, 機能
Integrated Processor Companion with Memory
High Integration Device Replaces Multiple Parts
Serial Nonvolatile Memory
Low Voltage Reset
Watchdog Timer
Early Power-Fail Warning/NMI
Two 16-bit Event Counters
Serial Number with Write-lock for Security
Processor Companion
Active-low Reset Output for VDD and Watchdog
Programmable VDD Reset Trip Point
Manual Reset Filtered and Debounced
Programmable Watchdog Timer
Dual Battery-backed Event Counter Tracks
System Intrusions or other Events
Comparator for Early Power-Fail Interrupt
64-bit Programmable Serial Number with Lock
The FM32xx is a family of integrated devices that
includes the most commonly needed functions for
processor-based systems. Major features include
nonvolatile memory available in various sizes, low-
VDD reset, watchdog timer, nonvolatile event counter,
lockable 64-bit serial number area, and general
purpose comparator that can be used for an early
power-fail (NMI) interrupt or other purpose. The
family operates from 2.7 to 5.5V.
The FM32xx family is software and pinout
compatible with the FM31xx family which also
includes a real-time clock. The common features
allow a system design that easily can be assembled
with or without timekeeping by simply selecting the
FM31xx or FM32xx, respectively.
Each FM32xx provides nonvolatile RAM available in
sizes including 4Kb, 16Kb, 64Kb, and 256Kb
versions. Fast write speed and unlimited endurance
allow the memory to serve as extra RAM or
conventional nonvolatile storage. This memory is
truly nonvolatile rather than battery backed.
The processor companion includes commonly needed
CPU support functions. Supervisory functions
include a reset output signal controlled by either a
low VDD condition or a watchdog timeout. /RST goes
This is a product in pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change
the specifications. Ramtron will issue a Product Change Notice if
any specification changes are made.
Rev 2.1
Dec. 2004
Ferroelectric Nonvolatile RAM
4Kb, 16Kb, 64Kb, and 256Kb versions
Unlimited Read/Write Endurance
10 year Data Retention
NoDelay™ Writes
Fast Two-wire Serial Interface
Up to 1 MHz Maximum Bus Frequency
Supports Legacy Timing for 100 kHz & 400 kHz
Device Select Pins for up to 4 Memory Devices
Companion Controlled via 2-wire Interface
Easy to Use Configurations
Operates from 2.7 to 5.5V
Small Footprint 14-pin SOIC (-S)
o “Green” 14-pin SOIC (-G)
Pin Compatible with FM31xx Series
Low Operating Current
-40°C to +85°C Operation
active when VDD drops below a programmable
threshold and remains active for 100 ms after VDD
rises above the trip point. A programmable watchdog
timer runs from 100 ms to 3 seconds. The watchdog
timer is optional, but if enabled it will assert the reset
signal for 100 ms if not restarted by the host before
the timeout. A flag-bit indicates the source of the
A general-purpose comparator compares an external
input pin to the onboard 1.2V reference. This is
useful for generating an early warning power-fail
interrupt (NMI) but can be used for any purpose. The
family also includes a programmable 64-bit serial
number that can be locked making it unalterable.
Additionally the FM32xx offers a dual event counter
that tracks the number of rising or falling edges
detected on dedicated input pins. The counter can
optionally be battery backed and even battery
operated by attaching a backup power source to the
VBAK pin. If VBAK is connected to a battery or
capacitor, then events will be counted even in the
absence of VDD.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Page 1 of 20

1 Page

FM32256 pdf, ピン配列
A1, A0
- 1.2V
2.5V -
LV Detect
Switched Power
Battery Backed
Figure 1. Block Diagram
Pin Descriptions
Pin Name
A0, A1
CNT1, CNT2 Input
Pin Description
Device select inputs are used to address multiple memories on a serial bus. To select
the device the address value on the two pins must match the corresponding bits
contained in the device address. The device select pins are pulled down internally.
Event Counter Inputs: These battery-backed inputs increment counters when an edge is
detected on the corresponding CNT pin. The polarity is programmable.
Power Fail Output: This is the early power-fail output.
Active low reset output with weak pull-up. Also input for manual reset.
Serial Data & Address: This is a bi-directional line for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the
part on the falling edge, and in on the rising edge. The SCL input also incorporates a
Schmitt trigger input for noise immunity.
Early Power-fail Input: Typically connected to an unregulated power supply to detect
an early power failure. This pin should not be left floating.
Backup supply voltage: A 3V battery or a large value capacitor. If VDD<3.6V and no
backup supply is used, this pin should be tied to VDD. If VDD>3.6V and no backup
supply is used, this pin should be left floating and the VBC bit should be set.
Supply Voltage.
Rev 2.1
Dec. 2004
Page 3 of 20


FM32256 電子部品, 半導体
NMI input
- 1.2V ref
Figure 5. Comparator as Early Power-Fail Warning
The comparator is a general purpose device and its
application is not limited to the NMI function.
Note: The maximum voltage on the comparator input PFI
is limited to 3.75V under normal operating conditions.
Event Counter
The FM32xx offers the user two battery-backed event
counters. Input pins CNT1 and CNT2 are
programmable edge detectors. Each clocks a 16-bit
counter. When an edge occurs, the counters will
increment their respective registers. Counter 1 is
located in registers 0Dh and 0Eh, Counter 2 is
located in registers 0Fh and 10h. These register
values can be read anytime VDD is above VTP, and
they will be incremented as long as a valid VBAK
power source is provided. To read, set the RC bit
register 0Ch bit 3 to 1. This takes a snapshot of all
four counter bytes allowing a stable value even if a
count occurs during the read. The registers can be
written by software allowing the counters to be
cleared or initialized by the system. Counts are
blocked during a write operation. The two counters
can be cascaded to create a single 32-bit counter by
setting the CC control bit (register 0Ch). When
cascaded, the CNT1 input will cause the counter to
increment. CNT2 is not used in this mode.
The control bits for event counting are located in
register 0Ch. Counter 1 Polarity is bit C1P, bit 0;
Counter 2 Polarity is C2P, bit 1; the Cascade Control
is CC, bit 2; and the Read Counter bit is RC bit 3.
16-bit Counter
16-bit Counter
Rev 2.1
Dec. 2004
Figure 6. Event Counter
The polarity bits must be set prior to setting the
counter value(s). If a polarity bit is changed, the
counter may inadvertently increment.
Serial Number
A memory location to write a 64-bit serial number is
provided. It is a writeable nonvolatile memory block
that can be locked by the user once the serial number
is set. The 8 bytes of data and the lock bit are all
accessed via the device ID for the processor
companion. Therefore the serial number area is
separate and distinct from the memory array. The
serial number registers can be written an unlimited
number of times, so these locations are general
purpose memory. However once the lock bit is set the
values cannot be altered and the lock cannot be
removed. Once locked the serial number registers can
still be read by the system.
The serial number is located in registers 11h to 18h.
The lock bit is SNL, register 0Bh bit 7. Setting the
SNL bit to a 1 disables writes to the serial number
registers, and the SNL bit cannot be cleared.
Backup Power
The event counter and battery-backed registers may
be powered with a backup power source. When the
primary system power fails, the voltage on the VDD
pin will drop. When VDD is less than 2.5V, the event
counters and battery-backed registers will switch to
the backup power supply on VBAK.
When a battery is used as a backup source, VDD must
be applied prior to inserting the battery to prevent
battery drain. Once VDD is applied and a battery is
inserted, the current drain on the battery is
guaranteed to be less than IBAK(max).
Trickle Charger
To facilitate capacitor backup the VBAK pin can
optionally provide a trickle charge current. When the
VBC bit, register 0Bh bit 2, is set to 1 the VBAK pin
will source approximately 15 µA until VBAK reaches
VDD or 3.75V whichever is less. In 3V systems, this
charges the capacitor to VDD without an external
diode and resistor charger. In 5V systems, it provides
the same convenience and also prevents the user from
exceeding the VBAK maximum voltage specification.
In the case where no battery is used, the VBAK pin
should be tied according to the following conditions:
For 3.3V systems, VBAK should be tied to VDD.
This assumes VDD does not exceed 3.75V.
For 5V systems, attach a 1 µF capacitor to VBAK
and turn the trickle charger on. The VBAK pin
will charge to the internal backup voltage which
regulates itself to about 3.6V. VBAK should not
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[ FM32256 データシート.PDF ]

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(FM3204 - FM32256) Integrated Processor Companion

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