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DAC104S085 の電気的特性と機能

DAC104S085のメーカーはNational Semiconductorです、この部品の機能は「10-Bit Micro Power QUAD Digital-to-Analog Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 DAC104S085
部品説明 10-Bit Micro Power QUAD Digital-to-Analog Converter
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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DAC104S085 Datasheet, DAC104S085 PDF,ピン配置, 機能
www.DataSheet4U.com
June 2006
DAC104S085
10-Bit Micro Power QUAD Digital-to-Analog Converter
with Rail-to-Rail Output
General Description
The DAC104S085 is a full-featured, general purpose QUAD
10-bit voltage-output digital-to-analog converter (DAC) that
can operate from a single +2.7V to 5.5V supply and uses
350 µA at 3V and 500 µA at 5V. The DAC104S085 is
packaged in a 10-lead MSOP package. The on-chip output
amplifier allows rail-to-rail output swing and the three wire
serial interface operates at clock rates up to 40 MHz over the
entire supply voltage range. Competitive devices are limited
to 25 MHz clock rates at supply voltages in the 2.7V to 3.6V
range. The serial interface is compatible with standard
SPI, QSPI, MICROWIRE and DSP interfaces.
The reference for the DAC104S085 serves all four channels
and can vary in voltage between 1V and VA, providing the
widest possible output dynamic range. The DAC104S085
has a 16-bit input shift register that controls the outputs to be
updated, the mode of operation, the powerdown condition,
and the binary input data. All four outputs can be updated
simultaneously or individually depending on the setting of
the two mode of operation bits.
A power-on reset circuit ensures that the DAC output powers
up to zero volts and remains there until there is a valid write
to the device. A power-down feature reduces power con-
sumption to less than a microWatt with three different termi-
nation options.
The low power consumption and small packages of the
DAC104S085 make it an excellent choice for use in battery
operated equipment.
The DAC104S085 is one of a family of pin compatible DACs,
including the 8-bit DAC084S085 and the 12-bit
DAC124S085. The DAC104S085 operates over the ex-
tended industrial temperature range of −40˚C to +105˚C.
Features
n Guaranteed Monotonicity
n Low Power Operation
n Rail-to-Rail Voltage Output
n Power-on Reset to 0V
n Simultaneous Output Updating
n Wide power supply range (+2.7V to +5.5V)
n Power Down Modes
Key Specifications
n Resolution
n INL
n DNL
n Settling Time
n Zero Code Error
n Full-Scale Error
n Supply Current
— Normal
— Pwr Down
10 bits
±2 LSB (max)
+0.35 / −0.25 LSB (max)
6 µs (max)
+15 mV (max)
−0.75 %FS (max)
485 µA (3.6V) / 650 µA (5.5V) max
20 nA (3.6V) / 30 nA (5.5V) typ
Applications
n Battery-Powered Instruments
n Digital Gain and Offset Adjustment
n Programmable Voltage & Current Sources
n Programmable Attenuators
Pin Configuration
20195302
SPIis a trademark of Motorola, Inc.
© 2006 National Semiconductor Corporation DS201953
www.national.com

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DAC104S085 pdf, ピン配列
Pin Descriptions
MSOP
Pin No.
1
2
3
4
5
6
Symbol
VA
VOUTA
VOUTB
VOUTC
VOUTD
GND
7 VREFIN
8 DIN
9 SYNC
10 SCLK
Type
Supply
Analog Output
Analog Output
Analog Output
Analog Output
Ground
Analog Input
Digital Input
Digital Input
Digital Input
Description
Power supply input. Must be decoupled to GND.
Channel A Analog Output Voltage.
Channel B Analog Output Voltage.
Channel C Analog Output Voltage.
Channel D Analog Output Voltage.
Ground reference for all on-chip circuitry.
Unbuffered reference voltage shared by all channels.
Must be decoupled to GND.
Serial Data Input. Data is clocked into the 16-bit shift
register on the falling edges of SCLK after the fall of
SYNC.
Frame synchronization input for the data input. When this
pin goes low, it enables the input shift register and data is
transferred on the falling edges of SCLK. The DAC is
updated on the 16th clock cycle unless SYNC is brought
high before the 16th clock, in which case the rising edge
of SYNC acts as an interrupt and the write sequence is
ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift
register on the falling edges of this pin.
3 www.national.com


3Pages


DAC104S085 電子部品, 半導体
A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release. The following specifica-
tions apply for VA = +2.7V to +5.5V, VREFIN = VA, RL = 2kto GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range
12 to 1011. Boldface limits apply for TMIN TA TMAX and all other limits are at TA = 25˚C, unless otherwise specified.
Symbol
Parameter
Conductions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
fSCLK
ts
SCLK Frequency
Output Voltage Settling Time
(Note 10)
100h to 300h code change
40 30 MHz (max)
4.5 6 µs (max)
SR Output Slew Rate
1 V/µs
Glitch Impulse
Code change from 200h to 1FFh
12
nV-sec
Digital Feedthrough
0.5 nV-sec
Digital Crosstalk
1 nV-sec
DAC-to-DAC Crosstalk
3 nV-sec
Multiplying Bandwidth
Total Harmonic Distortion
VREFIN = 2.5V ± 0.1Vpp
VREFIN = 2.5V ± 0.1Vpp
input frequency = 10kHz
160
70
kHz
dB
tWU
1/fSCLK
tCH
tCL
tSS
Wake-Up Time
SCLK Cycle Time
SCLK High time
SCLK Low Time
SYNC Set-up Time prior to SCLK
Falling Edge
VA = 3V
VA = 5V
0.8 µsec
0.5 µsec
25 33 ns (min)
7 10 ns (min)
7 10 ns (min)
4 10 ns (min)
Data Set-Up Time prior to SCLK
tDS Falling Edge
1.5 3.5 ns (min)
Data Hold Time after SCLK Falling
tDH Edge
1.5 3.5 ns (min)
tCFSR
tSYNC
SCLK fall prior to rise of SYNC
SYNC High Time
0 3 ns (min)
6 10 ns (min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified
Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input
current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the
operating ratings, or the power supply polarity is reversed).
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kresistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For example,
if VA is 3V, the digital input pins can be driven with a 5V logic device.
20195304
Note 8: To guarantee accuracy, it is required that VA and VREFIN be well bypassed.
Note 9: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
www.national.com
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共有リンク

Link :


部品番号部品説明メーカ
DAC104S085

10-Bit Micro Power QUAD Digital-to-Analog Converter

National Semiconductor
National Semiconductor
DAC104S085

DAC104S085/085-Q1 10-Bit Micro Pwr QUAD DAC w/Rail-to-Rail Output (Rev. F)

Texas Instruments
Texas Instruments
DAC104S085-Q1

DAC104S085/085-Q1 10-Bit Micro Pwr QUAD DAC w/Rail-to-Rail Output (Rev. F)

Texas Instruments
Texas Instruments


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