DataSheet.jp

CY7C1460AV33 の電気的特性と機能

CY7C1460AV33のメーカーはCypress Semiconductorです、この部品の機能は「(CY7C146xAV33) 36-Mbit Pipelined SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY7C1460AV33
部品説明 (CY7C146xAV33) 36-Mbit Pipelined SRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




このページの下部にプレビューとCY7C1460AV33ダウンロード(pdfファイル)リンクがあります。

Total 27 pages

No Preview Available !

CY7C1460AV33 Datasheet, CY7C1460AV33 PDF,ピン配置, 機能
www.DataSheet4U.com
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the
need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.2 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV33 and CY7C1462AV33 are available in
lead-free 100-pin TQFP and 165-Ball fBGA packages;
CY7C1464AV33 available in 209-Ball fBGA package
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V,
1 Mbit x 36 / 2 Mbit x 18 / 512K x72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They
are designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1460AV33/
CY7C1462AV33/CY7C1464AV33 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent Write/Read transitions.The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock input
is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1464AV33, BWa–BWd for CY7C1460AV33
and BWa–BWb for CY7C1462AV33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Logic Block Diagram-CY7C1460AV33 (1 Mbit x 36)
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05353 Rev. *A
Revised November 19, 2004

1 Page





CY7C1460AV33 pdf, ピン配列
Pin Configurations
PRELIMINARY
100-pin TQFP Packages
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1460AV33
(1 Mbit × 36)
80 DQPb NC 1
79 DQb NC 2
78 DQb NC 3
77 VDDQ VDDQ 4
76 VSS
VSS 5
75 DQb NC 6
74 DQb NC 7
73 DQb DQb 8
72 DQb DQb 9
71
70
VSS
VDDQ
VSS
VDDQ
10
11
69 DQb DQb 12
68 DQb DQb
67 VSS NC
66 NC
VDD
65 VDD NC
64 ZZ
VSS
63 DQa DQb
13
14
15
16
17
18
62 DQa DQb 19
61 VDDQ VDDQ 20
60 VSS
VSS
21
59 DQa DQb 22
58 DQa DQb 23
57 DQa DQPb 24
56 DQa NC 25
55 VSS
VSS 26
54 VDDQ VDDQ 27
53 DQa NC 28
52 DQa NC 29
51 DQPa NC 30
CY7C1462AV33
(2 Mbit × 18)
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPa
73 DQa
72 DQa
71 VSS
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSS
59 DQa
58 DQa
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document #: 38-05353 Rev. *A
Page 3 of 27


3Pages


CY7C1460AV33 電子部品, 半導体
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
CLK
Input-
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
Clock
CLK is only recognized if CEN is active LOW.
CE1
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device.
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.
CE3
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device.
OE
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
MODE
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by AX during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automat-
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,
DQPg is controlled by BWg, DQPh is controlled by BWh.
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
JTAG-Clock Clock input to the JTAG circuitry.
VDD
VDDQ
VSS
NC
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the device. Should be connected to ground of the system.
N/A No connects. This pin is not connected to the die.
NC/72M
N/A Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A Not connected to the die. Can be tied to any voltage level.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to Vss or left
floating.
Document #: 38-05353 Rev. *A
Page 6 of 27

6 Page



ページ 合計 : 27 ページ
 
PDF
ダウンロード
[ CY7C1460AV33 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
CY7C1460AV33

(CY7C146xAV33) 36-Mbit Pipelined SRAM

Cypress Semiconductor
Cypress Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap