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ADP3191 の電気的特性と機能

ADP3191のメーカーはAnalog Devicesです、この部品の機能は「Synchronous Buck Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADP3191
部品説明 Synchronous Buck Controller
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADP3191 Datasheet, ADP3191 PDF,ピン配置, 機能
www.DataSheet4U.com
6-Bit, Programmable 2-/3-/4-Phase,
Synchronous Buck Controller
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
±14.5 mV worst-case differential sensing error
over temperature
Logic-level PWM outputs for interface to external
high power drivers
PWM Flex-ModeTM architecture for excellent load
transient performance
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next-generation Intel® processors
VRM modules
Games consoles
GENERAL DESCRIPTION
The ADP3191/ADP3191A1 are highly efficient, multiphase,
synchronous buck switching regulator controllers optimized for
converting a 5 V or 12 V main supply into the core supply voltage
required by high performance Intel processors. They use an
internal 6-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 0.8375 V and 1.6 V. The devices use a multimode
PWM architecture to drive the logic-level outputs at a program-
mable switching frequency that can be optimized for VR size
and efficiency. The phase relationship of the output signals can
be programmed to provide 2-, 3-, or 4-phase operation, allowing
for the construction of up to four complementary buck
switching stages.
The ADP3191/ADP3191A also include programmable, no-load
offset and slope functions to adjust the output voltage as a function
of the load current, so it is always optimally positioned for a
system transient. The ADP3191/ADP3191A also provide
accurate and reliable short-circuit protection, adjustable current
limiting, and a delayed power good output that accommodates
on-the-fly output voltage changes requested by the CPU.
ADP3191
FUNCTIONAL BLOCK DIAGRAM
VCC
28
SHUNT
REGULATOR
(ADP3191 ONLY)
EN 11
GND 19
UVLO
SHUTDOWN
AND BIAS
DAC+150mV
CSREF
DAC–250mV
PWRGD 10
DELAY
RAMPADJ RT
14 13
OSCILLATOR
CMP
SET
RESET
EN
27 PWM1
CURRENT
BALANCING
CIRCUIT
CMP
CMP
RESET
2-/3-/4-PHASE
DRIVER LOGIC
RESET
26 PWM2
25 PWM3
CMP
RESET
24 PWM4
CROWBAR
CURRENT
LIMIT
ILIMIT 15
EN
DELAY 12
COMP 9
SOFT
START
CURRENT
LIMIT
CIRCUIT
23 SW1
22 SW2
21 SW3
20 SW4
17 CSSUM
16 CSREF
18 CSCOMP
8 FB
PRECISION
REFERENCE
VID
DAC
7
FBRTN
123456
VID4 VID3 VID2 VID1 VID0 VID5
Figure 1.
ADP3191/
ADP3191A
The ADP3191 is a replacement for the ADP3181. A built-in
shunt regulator allows the part to be connected to the 12 V
system supply through a series resistor.
The devices are specified over the commercial temperature
range of 0°C to 85°C and are available in a 28-lead TSSOP
and a 28-lead QSOP.
1 Protected by U. S. Patent Number 6,683,441; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

1 Page





ADP3191 pdf, ピン配列
ADP3191
SPECIFICATIONS
VCC = 5 V, FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.1
Table 1.
Parameter
ERROR AMPLIFIER
Output Voltage Range
Accuracy
Symbol
VCOMP
VFB
Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current, Input Voltage Low
Input Current, Input Voltage High
Pull-Up Resistance
Internal Pull-Up Voltage
VID Transition Delay Time 2
No CPU Detection Turn-Off Delay Time2
OSCILLATOR
Frequency Range2
Frequency Variation
ΔVFB
IFB
IFBRTN
IO(ERR)
GBW(ERR)
VIL(VID)
VIH(VID)
IIL(VID)
IIH(VID)
RVID
fOSC
fPHASE
Output Voltage
RAMPADJ Output Voltage
RAMPADJ Input Current Range
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Positioning Accuracy
Output Voltage Range
Output Current
CURRENT BALANCE CIRCUIT
Common-Mode Range
Input Resistance
Input Current
Input Current Matching3
CURRENT LIMIT COMPARATOR
Output Voltage
Normal Mode
In Shutdown
Output Current, Normal Mode
Maximum Output Current2
VRT
VRAMPADJ
IRAMPADJ
VOS(CSA)
IBIAS(CSSUM)
GBW(CSA)
ΔVFB
ICSCOMP
VSW(X)CM
RSW(X)
ISW(X)
ΔISW(X)
VILIMIT(NM)
VILIMIT(SD)
IILIMIT(NM)
Conditions
Relative to nominal DAC output, referenced
to FBRTN, CSSUM = CSCOMP
VCC = 4.75 V to 5.25 V
FB forced to VOUT – 3%
COMP = FB
CCOMP = 10 pF
VID(X) = 0 V
VID(X) = 1.25 V
VID code change to FB change
VID code change to 11111 to PWM going low
TA = +25°C, RT = 225 kΩ, 4-phase
TA = +25°C, RT = 100 kΩ, 4-phase
TA = +25°C, RT = 30 kΩ, 4-phase
RT = 100 kΩ to GND
RAMPADJ − FB
CSSUM – CSREF
CCSCOMP = 10 pF
CSSUM and CSREF
See Figure 5
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
EN > 0.8 V, RILIMIT = 250 kΩ
EN < 0.4 V, IILIMIT = −100 μA
EN > 0.8 V, RILIMIT = 250 kΩ
Min Typ Max Unit
0
−14.5
VCC V
+14.5 mV
0.05 %
14 15.5 17 μA
100 140 μA
500 μA
20 MHz
25 V/μs
0.4
0.8
–25 –35
5 15
35 60 85
1.0 1.2
400
400
V
V
μA
μA
V
ns
ns
0.25 2
155 200 245
400
600
1.8 2.0 2.3
–50 +50
0 100
MHz
kHz
kHz
kHz
V
mV
μA
–3 +3
–50 +50
10
10
03
–77 –80 –83
0.05 VCC
500
mV
nA
MHz
V/μs
V
mV
V
μA
–600
12
5
–5
20
11
+200
28
17
+5
mV
μA
%
2.8 3
3.3 V
400 mV
12 μA
60 μA
Rev. 0 | Page 3 of 28


3Pages


ADP3191 電子部品, 半導体
ADP3191
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
VID5 6
FBRTN 7
FB 8
COMP 9
PWRGD 10
EN 11
DELAY 12
RT 13
RAMPADJ 14
ADP3191/
ADP3191A
TOP VIEW
(Not to Scale)
28 VCC
27 PWM1
26 PWM2
25 PWM3
24 PWM4
23 SW1
22 SW2
21 SW3
20 SW4
19 GND
18 CSCOMP
17 CSSUM
16 CSREF
15 ILIMIT
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 6
VID4 to VID0,
VID5
Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1
if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from
0.8375 V to 1.6 V (see Table 2). Leaving all the VID pins open results in ADP3191/ADP3191A going into a
“No CPU” mode, shutting off their PWM outputs and pulling the PWRGD output low.
7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
8 FB
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no-load offset point.
9 COMP Error Amplifier Output and Compensation Point.
10 PWRGD Power Good Output. Open-drain output that signals when the output voltage is outside of the proper operating
range.
11 EN
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
12 DELAY
Soft Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time.
13 RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
14
RAMPADJ
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM
ramp.
15 ILIMIT
Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit threshold
of the converter. This pin is actively pulled low when the ADP3191/ADP3191A EN input is low or when VCC is
below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.
16 CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power good and crowbar functions. This pin should be connected to the common point of
the output inductors.
17 CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
18
CSCOMP
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of
the load line and the positioning loop response time.
19 GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23 SW4 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
24 to 27 PWM4 to
PMW1
Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3110A. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the
ADP3191/ADP3191A to operate as a 2-, 3-, or 4-phase controller.
28 VCC
ADP3191: A 240 Ω resistor should be placed between the 12 V system supply and the VCC pin to ensure 5 V.
ADP3191A: A 10 Ω resistor should be placed between the 5 V system supply and the VCC pin to ensure 5 V.
Rev. 0 | Page 6 of 28

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
ADP3190

6-Bit Programmable 2/3/4-Phase Synchronous Buck Controller

Analog Devices
Analog Devices
ADP3191

Synchronous Buck Controller

Analog Devices
Analog Devices
ADP3192

8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller

Analog Devices
Analog Devices
ADP3192A

8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller

Analog Devices
Analog Devices


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