

ADL5391のメーカーはAnalog Devicesです、この部品の機能は「DC to 2.0 GHz Multiplier」です。 
部品番号  ADL5391 
 
部品説明  DC to 2.0 GHz Multiplier  
メーカ  Analog Devices  
ロゴ  
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FEATURES
Ultrafast symmetric multiplier
Function: VW = α × (VX × VY)/1 V + VZ
Unique design ensures absolute XYsymmetry
Identical X and Y amplitude/timing responses
Adjustable gain scaling, α
DCcoupled throughout, 3 dB bandwidth of 2 GHz
Fully differential inputs, may be used single ended
Low noise, high linearity
Accurate, temperature stable gain scaling
Singlesupply operation (4.5 V to 5.5 V @ 130 mA)
Low current powerdown mode
16lead LFCSP
APPLICATIONS
Wideband multiplication and summing
High frequency analog modulation
Adaptive antennas (diversity/phased array)
Squarelaw detectors and true rms detectors
Accurate polynomial function synthesis
DC capable VGA with very fast control
GENERAL DESCRIPTION
The ADL5391 draws on three decades of experience in
advanced analog multiplier products. It provides the same
general mathematical function that has been field proven to
provide an exceptional degree of versatility in function synthesis.
VW = α × (VX × VY)/ 1 V + VZ
The most significant advance in the ADL5391 is the use of a
new multiplier core architecture, which differs markedly from
the conventional form that has been in use since 1970. The
conventional structure that employs a current mode, translinear
core is fundamentally asymmetric with respect to the X and Y
inputs, leading to relative amplitude and timing misalignments
that are problematic at high frequencies. The new multiplier
core eliminates these misalignments by offering symmetric
signal paths for both X and Y inputs. The Z input allows a signal
to be added directly to the output. This can be used to cancel a
carrier or to apply a static offset voltage.
The fully differential X, Y, and Z input interfaces are operational
over a ±2 V range, and they can be used in singleended fashion.
The user can apply a common mode at these inputs to vary
from the internally set VPOS/2 down to ground. If these inputs
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
DC to 2.0 GHz
Multiplier
ADL5391
FUNCTIONAL BLOCK DIAGRAM
YMNS YPLS
GADJ
XPLS
XMNS
ENBL
VMID
ADL5391
W = αXY/1V+Z
COMM VPOS
Figure 1.
ZMNS
ZPLS
WPLS
WMNS
are accoupled, their nominal voltage will be VPOS/2. These input
interfaces each present a differential 500 Ω input impedance up to
approximately 700 MHz, decreasing to 50 Ω at 2 GHz. The gain
scaling input, GADJ, can be used for fine adjustment of the gain
scaling constant (α) about unity.
The differential output can swing ±2 V about the VPOS/2
commonmode and can be taken in a singleended fashion as
well. The output common mode is designed to interface directly
to the inputs of another ADL5391. Light dc loads can be ground
referenced; however, accoupling of the outputs is recommended
for heavy loads.
The ENBL pin allows the ADL5391 to be disabled quickly to a
standby mode. It operates off supply voltages from 4.5 V to
5.5 V while consuming approximately 130 mA.
The ADL5391 is fabricated on Analog Devices proprietary, high
performance, 65 GHz, SOI complementary, SiGe bipolar IC
process. It is available in a 16lead, Pbfree, LFCSP and operates
over a −40°C to +85°C temperature range. Evaluation boards
are available.
One Technology Way, P.O. Box 9106, Norwood, MA 020629106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 Page ADL5391
SPECIFICATIONS
VPOS = 5 V, TA = 25°C, ZL = 50 Ω differential, ZPLS = ZMNS = open, GADJ = open, unless otherwise noted. Transfer function: W =
XY/1 V + Z, common mode internally set to 2.5 V nominal.
Table 1.
Parameter
MULTIPLICAND INPUTS (X, Y)
Differential Voltage Range
CommonMode Range
Input Offset Voltage
vs. Temperature
Differential Input Impedance
Fundamental Feedthrough, X or Y
Gain
DC Linearity
Scale Factor
CMRR
SUMMING INPUT (Z)
Differential Voltage Range
CommonMode Range
Gain
Differential Input Impedance
OUTPUTS (W)
Differential Voltage Range
CommonMode Output
Output Noise Floor
Output Noise Voltage Spectral Density
Output Offset Voltage
vs. Temperature
Differential Output Impedance
DYNAMIC CHARACTERISTICS
Frequency Range
Slew Rate
Settling Time
Second Harmonic Distortion
Third Harmonic Distortion
Conditions
XPLS, XMNS, YPLS, YMNS
Differential, common mode = 2.5 V
For full differential range
DC
−40°C to +85°C
f = dc
f = 2 GHz
f = 50 MHz, X (Y) = 0 V, Y (X) = 0 dBm, relative to
condition where X (Y) = 1 V
f = 1 GHz
X = 50 MHz and 0 dBm, Y = 1 V
X = 1 GHz and 0 dBm, Y = 1 V
X to output, Y = 1 V
X=Y=1V
±1 V pp, Y = 1 V, f = 50 MHz
ZPLS, ZMNS
Common mode from 2.5 V down to COMM
For full differential range
From Z to W, f ≤ 10 MHz, 0 dBm, X = Y = 1 V
f = dc
f = 2 GHz
WPLS, WMNS
No external common mode
X = Y = 1 V dc
f = 1 MHz
f = 1 GHz
X=Y=0
f = 1 MHz
f = 1 GHz
X = Y = 0, f = 1 MHz
Z = 0 V differential
f = dc
f = 200 MHz
f = 2 GHz
X, Y, Z to W
W from −2.0 V to +2.0 V, 150 Ω
X stepped from −1 V to +1 V, Z = 0 V, 150 Ω
X (Y) = 0 dBm, Y (X) = 1 V, fund = 10 MHz
Fund = 200 MHz
X (Y) = 0 dBm, Y (X) = 1 V, fund = 10 MHz
Fund = 200 MHz
Min Typ
Max Unit
2
0
20
±20
500
150
−42
−35
0.5
−1.33
1
1
42.1
V pp
2.5 V
mV
mV
Ω
Ω
dB
dB
dB
dB
% FS
V/V
dB
2
0
0.1
500
150
V pp
2.5 V
dB
Ω
Ω
±2
VPOS − 2.5
V
V
−133
−133
dBm/Hz
dBm/Hz
−138
−138
26.7
19
±19
0
75
500
dBm/Hz
dBm/Hz
nV/√Hz
mV
mV
Ω
Ω
Ω
0
8800
2.1
−60
−51
−61.5
−51.6
2 GHz
V/μs
ns
dBc
dBc
dBc
dBc
Rev. 0  Page 3 of 16
3Pages ADL5391
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMM 1
VPOS 2
VPOS 3
VPOS 4
PIN 1
INDICATOR
ADL5391
12 YMNS
11 YPLS
10 ZPLS
9 ZMNS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic
Description
1, 7 COMM
Device Common. Connect via lowest possible impedance to external circuit common.
2 to 4
VPOS
Positive Supply Voltage. 4.5 V to 5.5 V.
5, 6
WPLS, WMNS
Differential Outputs.
8 GADJ
Denominator Scaling Input.
9, 10 ZMNS, ZPLS Differential Intercept Inputs. Must be accoupled. Differential impedance 50 Ω nominal.
11, 12
YPLS, YMNS
Differential XMultiplicand Inputs.
13, 14
XPLS, XMNS
Differential YMultiplicand Inputs.
15 ENBL
Chip Enable. High to enable.
16 VMID
VPOS/2 Reference Output. Connect decoupling capacitor to circuit common.
Rev. 0  Page 6 of 16
6 Page  
ページ  合計 : 16 ページ  


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