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AD9254 の電気的特性と機能

AD9254のメーカーはAnalog Devicesです、この部品の機能は「14-Bit Analog to Digital Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD9254
部品説明 14-Bit Analog to Digital Converter
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD9254 Datasheet, AD9254 PDF,ピン配置, 機能
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FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input
SFDR = 84 dBc to 70 MHz input
Low power: 430 mW @ 150 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
CDMA2000, WCDMA, TD-SCDMA, and WiMax
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
Macro, micro, and pico cell infrastructure
GENERAL DESCRIPTION
The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS
analog-to-digital converter (ADC), featuring a high performance
sample-and-hold amplifier (SHA) and on-chip voltage reference.
The product uses a multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
150 MSPS data rates and guarantees no missing codes over the
full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9254 is suitable for applications in communications,
imaging, and medical ultrasound.
A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
14-Bit, 150 MSPS, 1.8 V
Analog-to-Digital Converter
AD9254
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9254
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
8
3
CORRECTION LOGIC
15
OUTPUT BUFFERS
REF
SELECT
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OR
DCO
D13 (MSB)
D0 (LSB)
SCLK/DFS
SDIO/DCS
CSB
AGND
CLK+ CLK–
Figure 1.
PDWN DRGND
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
The AD9254 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9254 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
2. The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
5. The AD9254 is pin-compatible with the AD9233, allowing
a simple migration from 12 bits to 14 bits.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

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AD9254 pdf, ピン配列
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AD9254
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance2
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1(DRVDD = 1.8 V)
IDRVDD1 (DRVDD = 3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input1 (DRVDD = 1.8 V)
Sine Wave Input1 (DRVDD = 3.3 V)
Standby Power3
Power-Down Power
Temperature Min
Full 14
AD9254BCPZ-150
Typ Max
Full Guaranteed
Full ±0.3 ±0.8
Full ±0.6 ±4.5
25°C ±0.4
Full ±1.0
25°C ±1.5
Full ±5.0
Full ±15
Full ±95
Full ±5 ±35
Full 7
25°C 1.3
Full 2
Full 8
Full 6
Full
1.7 1.8
1.9
Full
1.7 2.5
3.6
Full 240 260
Full 11
Full 23
Full 430 470
Full 450
Full 506
Full 40
Full 1.8
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
V
V
mA
mA
mA
mW
mW
mW
mW
mW
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).
Rev. 0 | Page 3 of 40


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AD9254 電子部品, 半導体
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AD9254
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
Parameter1
Temperature Min
AD9254BCPZ-150
Typ Max
CLOCK INPUT PARAMETERS
Conversion Rate, DCS Enabled
Full 20
150
Conversion Rate, DCS Disabled
Full 10
150
CLK Period
Full 6.7
CLK Pulse Width High, DCS Enabled
Full 2.0 3.3 4.7
CLK Pulse Width High, DCS Disabled
Full 3.0 3.3 3.7
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
Pipeline Delay (Latency)
Full 3.1 3.9 4.8
Full 4.4
Full 1.9 2.9
Full 3.0 3.8
Full 12
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
Full 0.8
Full 0.1
Full 350
OUT-OF-RANGE RECOVERY TIME
Full 3
SERIAL PORT INTERFACE4
SCLK Period (tCLK)
SCLK Pulse Width High Time (tHI)
SCLK Pulse Width Low Time (tLO)
SDIO to SCLK Setup Time (tDS)
SDIO to SCLK Hold Time (tDH)
CSB to SCLK Setup Time (tS)
CSB to SCLK Hold Time (tH)
Full 40
Full 16
Full 16
Full 5
Full 2
Full 5
Full 2
1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3 Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB.
4 See Figure 50 and the Serial Port Interface (SPI) section.
TIMING DIAGRAM
CLK+
CLK–
DATA
DCO
N+1
N+2
N
tA
tCLK
N+3
N+4
N+5
N+6
N+7
N+8
tPD
N – 13
tS
N – 12
N – 11
tH
N – 10 N – 9
tDCO
N–8
N–7
tCLK
N–6
N–5 N–4
Figure 2. Timing Diagram
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ps rms
μs
Cycles
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 6 of 40

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