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PDF HT49RV5 Data sheet ( Hoja de datos )
| Número de pieza | HT49RV5 | |
| Descripción | A/D | |
| Fabricantes | Holtek Semiconductor | |
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HT49RV5/HT49CV5
A/D With VFD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0077E HT49CVX Remote Control Receiver SWIP Design Note
- HA0078E HT49CVX Display SWIP Design Note
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· 20 bidirectional I/O lines (PA, PB, PC, PD)
· Two external interrupt inputs
· Two 16-bit programmable timer/event counters with
PFD (programmable frequency divider) function
· One 8-bit Remote Control Timer (RMT), pin-shared
with PC7
· Single channel serial interface
· VFD driver with 11´11 segments
(16-segment & 4-grid to 11-segment & 11-grid)
· 4K´16 program memory
· 192´8 data memory RAM
· Supports PFD for sound generation
· Real Time Clock (RTC)
· 8-bit prescaler for RTC
· Watchdog Timer
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· HALT function and wake-up feature reduce power
consumption
· 8-level subroutine nesting
· 4-channel 8-bit resolution A/D converter
· 2-channel 8-bit PWM output shared with 2 I/O lines
· Low voltage reset function
· Bit manipulation instruction
· 16-bit table read instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· 56-pin SSOP package
General Description
The HT49RV5/HT49CV5 are 8-bit high performance
single chip MCUs. Their single cycle instruction and
2-stage pipeline architecture make them suitable for
high speed applications. As the devices include an VFD
driver they are suitable for use in products which require
a front panel for their operation such as DVDs, VCDs,
Mini-component audio systems, cassette decks, tuners,
CD players, other home appliances, etc.
Rev. 1.20
1 April 14, 2006
1 page  
HT49RV5/HT49CV5
D.C. Characteristics
Ta=25°C
Symbol
Parameter
VDD Operating Voltage
Test Conditions
VDD Conditions
¾ fSYS=4MHz
¾ fSYS=8MHz
Min.
2.2
3.3
VEE VFD Supply Voltage
¾¾
0
IDD1
3V No load, ADC off, VFD off,
Operating Current (Crystal OSC) 5V fSYS=4MHz
¾
¾
IDD2
Operating Current (RC OSC)
3V No load, ADC off, VFD off,
5V fSYS=4MHz
¾
¾
IDD3
Operating Current
(fSYS=32768Hz)
3V
No load, ADC off, VFD off
5V
¾
¾
IDD4
3V No load, ADC off, VFD on,
Operating Current (Crystal OSC) 5V fSYS=4MHz
¾
¾
ISTB1 Standby Current (*fS=T1)
3V No load, system HALT
5V VFD off at HALT
¾
¾
ISTB2
Standby Current
(*fS=32768Hz OSC)
3V No load, system HALT
5V VFD off at HALT
¾
¾
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
3V
5V
¾
0
VIH1
Input High Voltage for I/O Ports, 3V
TMR and INT
5V
¾ 0.8VDD
VIL2 Input Low Voltage (RES)
3V
5V
¾
0
VIH2 Input High Voltage (RES)
3V
5V
¾ 0.9VDD
IOL I/O Port Sink Current
3V
VOL=0.1VDD
5V
6
10
IOH1 I/O Port Source Current
3V
VOH=0.9VDD
5V
-2
-5
IOH2 Grid Source Current
5V VOH=VDD-2V
IOH3 Segment Source Current
5V VOH=VDD-2V
RPH
Pull-high Resistance of I/O Ports 3V
and INT0, INT1
5V
¾
¾
-15
-3
20
10
RPL
VFD Driver Output Pull-low
Resistor
5V
¾
50
VLVR Low Voltage Reset Voltage
¾ LVR enabled
2.7
VAD A/D Input Voltage
¾¾
0
EAD A/D Conversion Error
3V
5V
¾
¾
IADC
Additional Power Consumption
if A/D Converter is Used
3V
No load
5V
¾
¾
Typ.
¾
¾
¾
2.0
5.0
1.8
4.6
1.2
4
3.5
7.5
¾
¾
4
14
¾
¾
¾
¾
12
25
-4
-8
¾
¾
60
30
100
3.0
¾
±0.5
1
2
Max.
5.5
5.5
VDD-30
3.0
8.0
2.7
7.5
2
7
4.5
12
1
2
10
20
0.2VDD
VDD
0.4VDD
VDD
¾
¾
¾
¾
¾
¾
100
50
150
3.3
VDD
±1
2
4
Unit
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
mA
mA
mA
mA
mA
mA
kW
kW
kW
V
V
LSB
mA
mA
Note: ²*fS² Refer to WDT clock option
Rev. 1.20
5 April 14, 2006
5 Page 
HT49RV5/HT49CV5
Interrupts
The HT49RV5/HT49CV5 provides two external inter-
rupts, two internal timer/event counter interrupts, three
remote control timer interrupts, an internal real time
clock interrupt and serial interface interrupt. The inter-
rupt control register 0 (INTC0;0BH) and interrupt control
register 1 (INTC1;1EH) both contain the interrupt control
bits that are used to set the enable/disable status and in-
terrupt request flags.
Once an interrupt subroutine is serviced, all other inter-
rupts are blocked (by clearing the EMI bit). This scheme
may prevent any further interrupt nesting. Other inter-
rupt requests may take place during this interval, but
only the interrupt request flag will be recorded. If another
interrupt requires servicing while the program is in the
interrupt service routine, the programmer should set the
EMI bit and the corresponding bit of the INTC0 or INTC1
to allow interrupt nesting. Once the stack is full, the inter-
rupt request will not be acknowledged, even if the related
interrupt is enabled, until the SP is decremented. If imme-
diate service is desired, the stack should be prevented
from becoming full.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the Program Counter onto the
stack followed by a branch to a subroutine at the speci-
fied location in the ROM. Only the contents of the Pro-
gram Counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the de-
sired control sequence, the contents should be saved in
advance.
External interrupts are triggered by an edge transition of
INT0 or INT1 (configuration option: high to low, low to
high, low to high or high to low), and the related interrupt
request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0)
is set as well. After the interrupt is enabled, the stack is
not full, and the external interrupt is active, a subroutine
call to location 04H or 08H occurs. The interrupt request
flag (EIF0 or EIF1) and EMI bits are all cleared to disable
other maskable interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 6 of INTC0), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 0CH occurs. The related inter-
rupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts.
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 4 of
INTC1) and its subroutine call location is 10H.
The Serial Interface interrupt is initialized by setting the
interrupt request flag (TRF; bit 5 of INTC1), which is
caused by completely receiving or transferring 8 bits of
data from a serial interface. After the interrupt is en-
abled, and the stack is not full, and the TRF bit is set, a
subroutine call to location 14H occurs. The related inter-
rupt request flag (TRF) is reset and the EMI bit is cleared
to disable further maskable interrupts.
The multi-function interrupt is initialized by setting the in-
terrupt request flag (MFF; bit 6 of INTC1), which is
caused by a regular real time clock signal, or caused by
a rising edge of RMT, or caused by a falling edge of
RMT, or caused by an RMT overflow. After the interrupt
is enabled, and the stack is not full, and the MFF bit is
set, a subroutine call to location 18H occurs. The related
interrupt request flag (MFF) is reset and the EMI bit is
cleared to disable further maskable interrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are both set to 1 (if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI sets the EMI bit and en-
ables an interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
Interrupt Source
Priority Vector
External interrupt 0
1 04H
External interrupt 1
2 08H
Timer/Event Counter 0 overflow
3
0CH
Timer/Event Counter 1 overflow
4
10H
Serial Interface interrupt
5 14H
Multi-function interrupt
6 18H
The RMT overflow interrupt flag (RMTVF; bit 0 of MFIS),
real time clock interrupt flag (RTF; bit 1 of MFIS), the
RMT rising edge interrupt flag (RMT0F; bit 2 of MFIS)
and the RMT falling edge interrupt flag (RMT1F; bit 3 of
MFIS) indicate that a related interrupt has occurred. Af-
ter reading these flags, these flags will not be cleared
automatically, they should be cleared by the user.
The serial interface interrupt is indicated by the interrupt
flag (TRF; bit 5 of INTC1), that is caused by receiving or
transferring a complete 8-bit data transfer between the
HT49RV5/ HT49CV5 and an external device. After the
interrupt is enabled (by setting ESBI; bit 1 of INTC1),
and the stack is not full, a subroutine call to location 14H
occurs. TRF is set by SIO and should be cleared by us-
ers.
The Timer/Event Counter 0 interrupt request flag (T0F),
external interrupt 1 request flag (EIF1), external inter-
rupt 0 request flag (EIF0), enable Timer/Event Counter0
Rev. 1.20
11 April 14, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT49RV5.PDF ] | |
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