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PDF ISPPAC-POWR1208 Data sheet ( Hoja de datos )
| Número de pieza | ISPPAC-POWR1208 | |
| Descripción | In-System Programmable Power Supply | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispPAC-® POWR1208
January 2004
In-System Programmable Power Supply
Sequencing Controller and Monitor
Data Sheet
Features
Application Block Diagram
■ Monitor and Control Multiple Power
Supplies
• Simultaneously monitors up to 12 power supplies
• Sequence controller for power-up conditions
• Provides eight output control signals
• Programmable digital and analog circuitry
-48V +
Primary
-
+5V
DC/DC +
Supply Gnd
-48V +
Primary
-
+3.3V
DC/DC +
Supply Gnd
RG
RG
+5V
Circuits
+3.3V
Circuits
■ Embedded PLD for Sequence Control
• Implements state machine and input conditional
events
• In-System Programmable (ISP™) through JTAG
and on-chip E2CMOS®
-48V +
Primary
-
+2.5V
DC/DC +
Supply Gnd
-48V +
Primary
-
+1.8V
DC/DC +
Supply Gnd
RG
RG
+2.5V
Circuits
+1.8V
Circuits
■ Embedded Programmable Timers
12 Analog Inputs
10uF
0.1uF
• 4 Programmable 8-bit timers (32µs to 524ms)
VDD VDDINP
• Programmable time delay between multiple
VMON1
VMON2
HVOUT1
HVOUT2
power supply ramp-up and wait statements
VMON3
VMON4
VMON5
HVOUT3
HVOUT4
OUT5
■ Analog Comparators for Monitoring
VMON6 ispPAC-POWR1208 OUT6
VMON7
OUT7
VMON8 Power Sequence OUT8
• 12 analog comparators for monitoring
VDD
VMON9
VMON10
VMON11
• 192 precise programmable threshold levels
VMON12
CLK
•
spanning 1.03V to 5.72V
Each comparator can be
independently
cDoantfiagS-heet4U.comIIRNNE12SET
ured around standard logic supply voltages of
IN3
IN4
Controller
Comp1
Comp2
Comp3
Comp4
Comp5
Comp6
Comp7
Comp8
POR
CREF
0.1uF
1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V
OE/EN
DC/DC Supply
or Regulator
OE/EN
DC/DC Supply
or Regulator
3.3V
3.3V
EN
Digital
Logic
EN
Digital
Logic
• Other user-defined voltages possible
• Eight direct comparator outputs
■ Embedded Oscillator
• Built-in clock generator, 250kHz
• Programmable clock frequency
• Programmable timer pre-scaler
• External clock support
Description
The Lattice ispPAC-POWR1208 incorporates both in-
system programmable logic and in-system programma-
ble analog circuits to perform special functions for
power supply sequencing and monitoring. The ispPAC-
■ Programmable Output Configurations
• Four digital outputs for logic and power supply
POWR1208 device has the capability to be configured
through software to control up to eight outputs for power
control
supply sequencing and 12 comparators monitoring sup-
• Four fully programmable gate driver outputs for ply voltage limits, along with four digital inputs for inter-
FET control, or programmable as four additional facing to other control circuits or digital logic. Once
digital outputs
configured, the design is downloaded into the device
• Expandable with ispMACH™ 4000 CPLD
■ 2.25V to 5.5V Supply Range
• In-system programmable at 3.0V to 5.5V
• Industrial temperature range: -40°C to +85°C
• Automotive temperature range: -40°C to +125°C
• 44-pin TQFP package
• Lead-free package option
through a standard JTAG interface. The circuit configu-
ration and routing are stored in non-volatile E2CMOS.
PAC-Designer,® an easy-to-use Windows-compatible
software package gives users the ability to design the
logic and sequences that control the power supplies or
FET driver circuits. The user has control over timing
functions, programmable logic functions and compara-
tor threshold values as well as I/O configurations.
DataShee
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
DataSheet4Ubra.cndoomr product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
1
pwr1208_04
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Lattice Semiconductor
ispPAC-POWR1208 Data Sheet
Recommended Operating Conditions
Symbol
Parameter
Conditions
Min.
Max. Units
VDD
VDDPROG1
VDDINP2
VIN3
VMON
Core supply voltage at pin
Core supply voltage at pin
Digital input supply voltage for IN1-IN4
Input voltage digital inputs
Voltage monitor inputs VMON1 - VMON12
Erase/Program
Cycles
During E2 cell programming
EEPROM, programmed at
VDD = 3.0V to 5.5V
-40°C to +85°C
2.25
3.0
2.25
0
0
1000
5.5 V
5.5 V
5.5 V
5.5 V
6.0 V
— Cycles
TAPROG
Ambient temperature during
programming
-40 +85 °C
TA Ambient temperature
Power applied - Industrial
Power applied - Automotive
-40 +85
-40 +125
°C
°C
1. The ispPAC-POWR1208 device must be powered from 3.0V to 5.5V during programming of the E2CMOS memory.
2. VDDINP is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the VDDINP pin with appropriate
supply voltage for the given input logic range.
3. Digital inputs are tolerant up to 5.5V, independent of the VDDINP voltage.
Analog Specifications
Over Recommended Operating Conditions
et4U.com
Symbol
IDD
Reference
Parameter
Supply Current
Conditions
Internal Clock = 250kHz
DataSheet4U.com
Min.
—
Typ.
7
Max.
15
Units
mA
Symbol
Parameter
VREF1
Reference voltage at CREF pin
1. CREF pin requires a 0.1µF capacitor to ground.
Conditions
T = 25°C
Min.
—
Typ.
1.17
Max.
—
Units
V
Voltage Monitors
Symbol
RIN
VMON Range
VMON Accuracy
VMON Tempco1
HYST
Parameter
Conditions
Input impedance
Programmable voltage monitor trip
point (192 steps)
Absolute accuracy of any trip point
Temperature drift of any trip point
T = 25 °C,
VDD = 3.3V
-40°C to +85°C
-40°C to +125°C
Hysteresis of VMON input,
VDD = 3.3V
VHYST = HYST*VMON (+/-3 to +/-13mV)
PSR
Trip point sensitivity to VDD
1. See typical performance curves.
VDD = 3.3V
Min.
70
1.03
Typ.
100
Max.
130
5.72
Units
kΩ
V
-0.9 +0.9
50
76
+/- 0.3% of
trip point
setting
0.06
%
ppm/ °C
ppm/ °C
%
%/V
DataShee
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ispPAC-POWR1208 Data Sheet
Table 1. VMON Trip Point Table1
1.2 low 1.2 high 1.5 low 1.5 high 1.8 low 1.8 high 2.5 low
1.036 1.202 1.291 1.502 1.549 1.801 2.153
1.046 1.213 1.303 1.516 1.564 1.818 2.173
1.056 1.225 1.316 1.531 1.579 1.836 2.195
1.066 1.237 1.329 1.546 1.595 1.854 2.216
1.076 1.249 1.341 1.560 1.609 1.871 2.237
1.087 1.261 1.354 1.575 1.625 1.889 2.258
1.096 1.272 1.366 1.590 1.639 1.906 2.279
1.107 1.284 1.379 1.605 1.655 1.924 2.300
1.117 1.295 1.391 1.619 1.669 1.941 2.320
1.127 1.307 1.404 1.634 1.685 1.959 2.342
1.137 1.319 1.417 1.649 1.700 1.977 2.363
1.147 1.331 1.429 1.663 1.715 1.994 2.384
1.157 1.343 1.442 1.678 1.730 2.012 2.405
1.168 1.355 1.455 1.693 1.746 2.030 2.427
1.178 1.366 1.467 1.707 1.761 2.047 2.447
1.188 1.378 1.480 1.722 1.776 2.065 2.469
1.All possible comparator trip voltages using internal attenuation settings.
2.5 high
2.500
2.524
2.549
2.574
2.597
2.622
2.646
2.671
2.694
2.719
2.744
2.768
2.793
2.818
2.841
2.866
3.3 low
2.842
2.869
2.897
2.926
2.952
2.981
3.008
3.036
3.063
3.091
3.120
3.147
3.175
3.203
3.230
3.259
3.3 high
3.297
3.328
3.361
3.394
3.425
3.458
3.489
3.522
3.553
3.586
3.619
3.650
3.683
3.716
3.747
3.780
5.0 low
4.299
4.340
4.383
4.426
4.466
4.509
4.550
4.593
4.633
4.676
4.719
4.760
4.803
4.846
4.886
4.929
5.0 high
4.991
5.038
5.088
5.138
5.185
5.235
5.282
5.332
5.379
5.429
5.479
5.526
5.576
5.626
5.673
5.723
et4U.com
Table 1 shows all possible comparator trip point voltage settings. The internal resistive divider allows ranges for
1.2V, 1.8V, 2.5V, 3.3V and 5.0V. There are 192 available voltages, ranging from 1.036V to 5.723V. In addition to the
192 voltage monitor trip points, the user can addDadtadSithioeneatl4rUe.sciostmors outside the device to divide down the voltage
and achieve virtually any voltage trip point. This allows the capability to monitor higher voltages such and 12V, 15V,
24V, etc. Voltage monitor trip points are set in the graphical user interface of PAC-Designer software by simple pull-
down menus. The user simply selects the given range and corresponding trip point value. Attenuation and refer-
ence values are set internally using E2CMOS configuration bits internal to the device.
DataShee
Figure 2 shows a single comparator, the attenuation network and reference used to program the monitor trip points.
Each of the twelve comparators are independently set in the same way.
Theory Of Operation
The ispPAC-POWR1208 incorporates programmable voltage monitors along with digital inputs and outputs as well
as high voltage FET gate drivers to control MOSFETs for ramping up power supply rails. The 16 macrocell PLD
inputs are from the 12 voltage monitors and four digital inputs. There are four embedded programmable timers that
interface with the PLD, along with an internal programmable oscillator.
The 12 independently programmable voltage monitors each have 192 programmable trip points.
Figure 2 shows a simplified schematic representation of one of these monitors.
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