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PDF MSM5764802 Data sheet ( Hoja de datos )
| Número de pieza | MSM5764802 | |
| Descripción | (MSM5718C50 / MSM5764802) 18Mb (2M x 9) & 64Mb (8M x 8) Concurrent RDRAM | |
| Fabricantes | OKI electronic componets | |
| Logotipo |  |
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E2G1059-39-21
¡ Semiconductor¡ Semiconductor
MSTMh5is7v1e8rCsi5o0n/:MFDeb5.7169498902
Previous version: Nov. 1998
MSM5718C50/MD5764802
18Mb (2M ¥ 9) & 64Mb (8M ¥ 8) Concurrent RDRAM
DESCRIPTION
The 18/64-Megabit Concurrent Rambus™ DRAMs (RDRAM®) are extremely high-speed
CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits. They are capable of bursting unlimited
lengths of data at 1.67 ns per byte (13.3 ns per eight bytes). The use of Rambus Signaling Level (RSL)
technology permits 600 MHz transfer rates while using conventional system and board design
methodologies. Low effective latency is attained by operating the two or four 2KB sense amplifiers
as high speed caches, and by using random access mode (page mode) to facilitate large block
transfers. Concurrent (simultaneous) bank operations permit high effective bandwidth using
interleaved transactions.
RDRAMs are general purpose high-performance memory devices suitable for use in a broad range
of applications including PC and consumer main memory, graphics, video, and any other
application where high-performance at low cost is required.
FEATURES
• Compatible with Base RDRAMs
• 600 MB/s peak transfer rate per RDRAM
• Rambus Signaling Level (RSL) interface
• Synchronous, concurrent protocol for block-oriented, interleaved (overlapped) transfers
• 480 MB/s effective bandwidth for random 32 byte transfers from one RDRAM
• 13 active signals require just 32 total pins on the controller interface (including power)
• 3.3 V operation
• Additional/multiple Rambus Channels each provide an additional 600 MB/s bandwidth
• Two or four 2KByte sense amplifiers may be operated as caches for low latency access
• Random access mode enables any burst order at full bandwidth within a page
• Graphics features include write-per-bit and mask-per-bit operations
• Available in horizontal surface mount plastic package (SHP32-P-1125-0.65-K)
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¡ Semiconductor
MSM5718C50/MD5764802
GENERAL DESCRIPTION
Figure 3 is a block diagram of an RDRAM. At the bottom is a standard DRAM core organized as two
or four independent banks, with each bank organized as 512 or 1024 rows, and with each row
consisting of 2KBytes of memory cells. One row of a bank may be “activated” at any time (ACTV
command) and placed in the 2KByte “page” for the bank. Column accesses (READ and WRITE
commands) may be made to this active page.
The smallest block of memory that may be accessed with READ and WRITE commands is an octbyte
(eight bytes). Bitmask and bytemask options are available with the WRITE command to allow finer
write granularity. There are six control registers that are accessed at initialization time to configure
the RDRAM for a particular application.
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5 Page 
¡ Semiconductor
MSM5718C50/MD5764802
Table 4 Command Encoding
ACTV AUTO OP5 OP4 OP3 OP2 OP1 OP0 Command
0 0 0 0 0 X 0 0 READ
0 0 b1 b0 D B 0 1 WRITE
0 0 0 0 0 1 1 0 RREG
0 0 0 0 D 1 1 1 WREG
0 1 0 0 0 X 0 0 READA
0 1 b1 b0 D B 0 1 WRITEA
1 0 0 0 0 X 0 0 ACTV/READ
1 0 b1 b0 D B 0 1 ACTV/WRITE
1 1 0 0 0 X 0 0 ACTV/READA
1 1 b1 b0 D B 0 1 ACTV/WRITEA
1 0 0 0 0 X 0 0 PRE/ACTV/READ
1 0 b1 b0 D B 0 1 PRE/ACTV/WRITE
1 1 0 0 0 X 0 0 PRE/ACTV/READA
1 1 b1 b0 D B 0 1 PRE/ACTV/WRITEA
Description
Read
Write (b1, b0, B masking and D broadcast options)
Register Read
Register Write (D)
Read/AutoPrecharge
Write/AutoPrecharge (b1, b0, D, B)
Activate/Read
Activate/Write (b1, b0, D, B)
Activate/Read/AutoPrecharge
Activate/Write/AutoPrecharge (b1, b0, D, B)
Precharge/Activate/Read
Precharge/Activate/Write (b1, b0, D, B)
Precharge/Activate/Read/AutoPrecharge
Precharge/Activate/Write/AutoPrecharge (b1, b0, D, B)
11/45
11 Page | ||
| Páginas | Total 46 Páginas | |
| PDF Descargar | [ Datasheet MSM5764802.PDF ] | |
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