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PDF LT1575CS8-5 Data sheet ( Hoja de datos )

Número de pieza LT1575CS8-5
Descripción Ultrafast Transient Response/ Low Dropout Regulators Adjustable and Fixed
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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LT1575/LT1577
Ultrafast Transient Response,
Low Dropout Regulators
Adjustable and Fixed
FEATURES
s UltraFastTM Transient Response Eliminates
Tantalum and Electrolytic Output Capacitors
s FET RDS(ON) Defines Dropout Voltage
s 1% Reference/Output Voltage Tolerance Over
Temperature
s Typical Load Regulation: 1mV
s High Side Sense Current Limit
s Multifunction Shutdown Pin with Latchoff
U
APPLICATIONS
s Pentium® Processor Supplies
s PowerPCTM Supplies
s 5V to 3.XXV or 3.3V to 2.XXV Microprocessor Supplies
s GTL Termination
s Low Voltage Logic Supplies
LT1575CN8/LT1575CS8
LT1575CN8-1.5/LT1575CS8-1.5
LT1575CN8-2.8/LT1575CS8-2.8
LT1575CN8-3.3/LT1575CS8-3.3
LT1575CN8-3.5/LT1575CS8-3.5
LT1575CN8-5/LT1575CS8-5
LT1577CS-ADJ/ADJ
LT1577CS-3.3/ADJ
LT1577CS-3.3/2.8
Adjustable
1.5V Fixed
2.8V Fixed
3.3V Fixed
3.5V Fixed
5V Fixed
Adjustable, Adjustable
3.3V Fixed, Adjustable
3.3V Fixed, 2.8V Fixed
Consult factory for additional output voltage combinations available
in the LT1577.
DESCRIPTION
The LT®1575/LT1577 are single/dual controller ICs that
drive low cost external N-channel MOSFETs as source
followers to produce ultrafast transient response, low
dropout voltage regulators.
The LT1575/LT1577 achieve unprecedented transient-
load performance by eliminating expensive tantalum or
bulk electrolytic output capacitors in the most demanding
modern microprocessor applications. Precision-trimmed
adjustable and fixed output voltage versions accommo-
date any required microprocessor power supply voltage.
Selection of the N-channel MOSFET RDS(ON) allows very
low dropout voltages to be achieved.
Unique protection features include a high side current
limit amplifier that activates a fault protection timer
circuit. A multifunction Shutdown pin provides either
current limit time-out with latchoff, overvoltage protec-
tion, thermal shutdown or a combination of these func-
tions. The LT1575 is available in 8-pin SO or PDIP and the
LT1577 is available in 16-pin narrow body SO.
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
TYPICAL APPLICATION
Ultrafast Transient Response 5V to 3.3V Low Dropout Regulator
(For Schematic Including Current Limit, See Typical Applications)
*FOR T < 45°C:
C6 = 24 × 1µF Y5V
CERAMIC SURFACE
MOUNT CAPACITORS.
FOR T > 45°C:
C6 = 24 × 1µF X7R
CERAMIC SURFACE
MOUNT CAPACITORS.
PLACE C6 IN THE
MICROPROCESSOR
SOCKET CAVITY
12V
1
2
C2
1µF 3
4
LT1575-3.3
SHDN IPOS
VIN INEG
GND GATE
OUT COMP
8
7
6
5
R2
5
C3
10pF
R1
7.5k
C4
1000pF
+
Q1
IRFZ24
5V
C5
220µF
C6*
24µF
VOUT
3.3V
5A
GND
1575/77 TA01
Transient Response for
0.2A to 5A Output Load Step
50mV/DIV
2A/DIV
100µs/DIV
1575/77 TA02
1

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LT1575CS8-5 pdf
TYPICAL PERFORMANCE CHARACTERISTICS
LT1575/LT1577
VREF/VOUT Line Regulation
vs Temperature
0.030
0.025
0.020
0.015
0.010
0.005
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G10
Error Amplifier Large-Signal
Voltage Gain vs Temperature
120
115
110
105
100
95
90
85
80
75
70
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G11
Gain and Phase vs Frequency
200
150
PHASE
100
GAIN
50
0
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
1575/77 G12
Gate Output Swing Low
vs Temperature
3.00
ILOAD = 50mA
2.75
2.50
NO LOAD
2.25
2.00
1.75
1.50
1.25
Gate Output Swing High
vs Temperature
3.0
2.5
2.0
ILOAD = 50mA
1.5
1.0
NO LOAD
0.5
IPOS + INEG Supply Current
vs Temperature
1000
900
800 IPOS = INEG = 5V
IPOS = INEG = 12V
700 IPOS = INEG = 20V
600 IPOS = INEG = 3V
500
400
1.00
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G13
0
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G14
300
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G15
Current Limit Threshold Voltage
vs Temperature
65
Current Limit Threshold Voltage
Line Regulation vs Temperature
0
60
55 IPOS = 5V
IPOS = 3V
50
IPOS = 20V
45
40
– 0.1
– 0.2
– 0.3
– 0.4
35
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G16
– 0.5
–75 – 50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
1575/77 G17
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LT1575CS8-5 arduino
LT1575/LT1577
APPLICATIONS INFORMATION
Reference voltage accuracy for the adjustable version and
output voltage accuracy for the fixed voltage versions are
specified as ±0.6% at room temperature and as ±1% over
the full operating temperature range. This places the
LT1575/LT1577 family among a select group of regulators
with a very tightly specified output voltage tolerance. The
accurate 1.21V reference is tied to the noninverting input
of the main error amplifier in the feedback control loop.
The error amplifier consists of a single high gain gm stage
with a transconductance equal to 15 millimhos. The
inverting terminal is brought out as the FB pin in the
adjustable voltage version and as the OUT pin in fixed
voltage versions. The gm stage provides differential-to-
single ended conversion at the COMP pin. The output
impedance of the gm stage is about 1Mand thus, 84dB
of typical DC error amplifier open-loop gain is realized
along with a typical 75MHz uncompensated unity-gain
crossover frequency. Note that the overall feedback
loop’s DC gain decreases from the gain provided by the
error amplifier by the attenuation factor in the resistor
divider network which sets the DC output voltage. These
attenuation factors are already built into the Open-Loop
Voltage Gain specifications for the LT1575 fixed voltage
versions in the Electrical Characteristics table to simplify
user calculations. External access to the high impedance
gain node of the error amplifier permits typical loop
compensation to be accomplished with a series RC
network to ground.
A high speed, high current output stage buffers the COMP
node and drives up to 5000pF of “effective” MOSFET gate
capacitance with almost no change in load transient per-
formance. The output stage delivers up to 50mA peak
when slewing the MOSFET gate in response to load
current transients. The typical output impedance of the
GATE pin is typically 2. This pushes the pole due to the
error amplifier output impedance and the MOSFET input
capacitance well beyond the loop crossover frequency. If
the capacitance of the MOSFET used is less than 1500pF,
it may be necessary to add a small value series gate
resistor of 2to 10. This gate resistor helps damp the
LC resonance created by the MOSFET gate’s lead induc-
tance and input capacitance. In addition, the pole formed
by this resistance and the MOSFET input capacitance can
be fine tuned.
Because the MOSFET pass transistor is connected as a
source follower, the power path gain is much more pre-
dictable than designs that employ a discrete PNP transis-
tor as the pass device. This is due to the significant
production variations encountered with PNP Beta.
MOSFETs are also very high speed devices which enhance
the ability to produce a stable wide bandwidth control
loop. An additional advantage of the follower topology is
inherently good line rejection. Input supply disturbances
do not propagate through to the output. The feedback loop
for a regulator circuit is completed by providing an error
signal to the FB pin in the adjustable voltage version and
the OUT pin in the fixed voltage version. In both cases, a
resistor divider network senses the output voltage and
sets the regulated DC bias point. In general, the LT1575
regulator feedback loop permits a loop crossover fre-
quency on the order of 1MHz while maintaining good
phase and gain margins. This unity-gain frequency is a
factor of 20 to 30 times the bandwidth of currently
implemented regulator solutions for microprocessor power
supplies. This significant performance benefit is what
permits the elimination of all bulk output capacitance.
Several other unique features are included in the design
that increase its functionality and robustness. These func-
tions comprise the remainder of the block diagram.
A high side sense, current limit amplifier provides active
current limiting for the regulator. The current limit ampli-
fier uses an external low value shunt resistor connected in
series with the external MOSFET’s drain. This resistor can
be a discrete shunt resistor or can be manufactured from
a Kelvin-sensed section of “free” PC board trace. All load
current flows through the MOSFET drain and thus, through
the sense resistor. The advantage of using high side
current sensing in this topology is that the MOSFET’s gain
and the main feedback loop’s gain remain unaffected. The
sense resistor develops a voltage equal to IOUT(RSENSE).
The current limit amplifier’s 50mV threshold voltage is a
good compromise between power dissipation in the sense
resistor, dropout voltage impact and noise immunity.
Current limit activates when the sense resistor voltage
equals the 50mV threshold.
Two events occur when current limit activates: the first is
that the current limit amplifier drives Q2 in the block
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