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PDF LT1573CS8 Data sheet ( Hoja de datos )
| Número de pieza | LT1573CS8 | |
| Descripción | Low Dropout PNP Regulator Driver | |
| Fabricantes | Linear Technology | |
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FEATURES
s Low Cost Solution for High Current, Low Dropout
Regulators
s Fast Transient Response Needs Much Less
Bulk Capacitance
s Latching Overload Protection Minimizes
Heat Sink Size
s Precision Output Voltage (1%)
s Single Supply Operation: VIN = 2.8V to 10V
s Small Surface Mount Package
s Capable of Very Low Dropout Voltage (<0.2V)
s Fixed or Adjustable Outputs
s Shutdown
U
APPLICATIO S
s 3.3V to 2.5V Regulators
s Microprocessor Power Sources
s Post Regulator for Switching Supplies
s High Efficiency Linear Regulators
s Ultralow Dropout Regulators
s Low Voltage Linear Regulators
, LTC and LT are registered trademarks of Linear Technology Corporation.
LT1573
Low Dropout
PNP Regulator Driver
DESCRIPTIO
The LT ®1573 is a regulator driver IC designed to provide
a low cost solution for applications requiring high current,
low dropout and fast transient response. When combined
with an external PNP power transistor, this device pro-
vides load current up to 5A with dropout voltages as low
as 0.35V. The LT1573 circuitry is designed for extremely
fast transient response. This greatly reduces bulk storage
capacitance when the regulator is used in applications
with fast, high current load transients.
To keep cost and complexity low, the LT1573 uses a new
time-delayed latching overcurrent protection technique
that requires no external current sense resistor. Base drive
is limited for instantaneous protection, and a time-delayed
latch protects the regulator from continuous short
circuits.
The LT1573 is available as an adjustable regulator with an
output range of 1.27V to 6.8V and with fixed output
voltages of 2.5V, 2.8V and 3.3V. Output accuracy is better
than 1% to meet the critical regulation requirement of fast
microprocessors. A special 8-pin, fused-lead surface mount
package is used to minimize regulator footprint and pro-
vide adequate heat sinking.
TYPICAL APPLICATIO
FB COMP
CC
100pF
RC
1k
+
CTIME
VIN
5V
LATCH
VOUT
LT1573
SHDN
VIN
GND DRIVE
CIN
100µF
TANT
RD RB
24Ω 50Ω
QOUT
MOTOROLA
D45H11
+
COUT1
1µF
+
CER
× 24
COUT2
220µF
TANT
R1
1.6k
R2
1k
LOAD
VOUT = 1.265V (1 + R1/R2)
FOR T < 45°C, COUT1 = 24 × 1µF Y5V CERAMIC SURFACE MOUNT CAPACITORS.
FOR T > 45°C, COUT1 = 24 × 1µF X7R CERAMIC SURFACE MOUNT CAPACITORS.
PLACE COUT1 IN THE MICROPROCESSOR SOCKET CAVITY
Figure 1. 3.3V, 5A Microprocessor Supply
VOUT
3.3V
GND
1573 F01
Transient Response for
0.2A to 5A Output Load Step
50mV/DIV
2.5A/DIV
10µs/DIV
1573 F01a
1
1 page  
LT1573
PI FU CTIO S
FB (Pin 1): The feedback pin is the inverting input of the
error amplifier. The noninverting input of the error ampli-
fier is internally connected to a 1.265V reference. The error
amplifier will servo the drive to the output transistor, QOUT
in Figure 1, to force the voltage at the feedback pin to be
1.265V. Output voltage is set by a resistor divider as
shown in Figure 1. For adjustable devices an external
resistor divider is used to set the output voltage. For fixed
voltage devices the resistor divider is internal and the top
of the resistor divider is connected to the VOUT pin.
LATCH (Pin 2): The LT1573 provides overcurrent protec-
tion with a timed latch-off circuit. The latch-off time out is
triggered when the DRIVE pin is pulled below the satura-
tion voltage of the drive transistor. The saturation voltage
is a function of the drive current and is equal to approxi-
mately 130mV at 20mA rising to 780mV at 250mA (see
typical performance curves). The time out is set by the
latch charging current and the value of a capacitor con-
nected between the LATCH pin and ground. If the
overcurrent condition persists at the end of the timing
cycle the regulator will latch off until either the latch is reset
or power is cycled off and back on. The latch can be reset
by either pulling the SHDN pin high, pulling current out of
the LATCH pin greater than latching current or grounding
the LATCH pin. Exceeding the thermal limit temperature
will trigger the latch with no timing delay. Under normal
condition, the DC voltage at the LATCH pin is zero. When
the system is latched off, the DC voltage at theLATCH pin
is two VBE above ground.
SHDN (Pin 3): The SHDN pin has two functions. It can be
used to turn off the output voltage by disabling the drive to
the output transistor. It can also be used to reset the
current limit latch. The shutdown/reset functions are
activated by applying a voltage > 1.3V to the SHDN pin. The
output voltage will restart as soon as the SHDN pin is
pulled below the shutdown threshold. If the shutdown/
reset function is not used, the pin should be grounded. The
voltage applied to the SHDN pin can be higher than the
input voltage. When the SHDN pin voltage is higher than
2V, the SHDN pin current increases and is limited by an
internal 20k resistor.
GND (Pin 4): Circuit Ground.
DRIVE (Pin 5): The DRIVE pin is connected to the collector
of the main drive transistor of the LT1573. This drive
transistor sinks the base current of the external PNP
output transistor. A resistor is normally inserted between
the base of the external PNP output transistor and the
DRIVE pin. This resistor is sized to allow the LT1573 to
sink the appropriate amount of base current for a given
application and to activate the overcurrent latch in a fault
condition.
VIN (Pin 6): This pin provides power to all internal circuitry
of the LT1573 including bias, start-up, thermal limit, error
amplifier and all overcurrent latch circuitry.
VOUT (Pin 7): The VOUT pin is the input to comparator C1
shown in Block Diagram. This pin is normally connected
to the output. The comparator C1 is used to disable the
overcurrent latch during start-up when the output transis-
tor is saturated. For fixed voltage devices the top of the
internal resistor divider that sets the output voltage is
connected to this pin.
COMP (Pin 8): A compensation network is inserted
between the VOUT and COMP pins to obtain optimal
transient response. Under normal condition, the DC volt-
age of the COMP pin sits at one VBE above ground.
5
5 Page 
LT1573
APPLICATIO S I FOR ATIO
capabilities of the PC board and its copper traces. Table
3 lists some typical values for the thermal resistance of
the LT1573. Measured values of thermal resistance for
a specific board size with different copper areas are
listed. All measurements were taken in still air on 3/32"
FR-4 board with 2oz copper. It is possible to achieve
significantly lower values with thinner multilayer boards.
Table 3. LT1573 Thermal Resistance
COPPER AREA
THERMAL RESISTANCE
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm2
1000mm2
225mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
80°C/W
80°C/W
85°C/W
*Device is mounted on topside.
We can find out the maximum junction temperature of
the LT1573 during normal load operation after we
calculate the maximum power dissipation of the LT1573
from Eq (2). From the previous design example, the
maximum power dissipation of the LT1573 is 0.2W.
From Table 3, we know the thermal resistance from
junction-to-ambient is around 85°C/W. The tempera-
ture difference between junction and ambient is:
(0.25W)(85°C/W) = 21.25°C
If the maximum ambient temperature is specified at
50°C, the maximum junction temperature will be:
TJMAX = 50°C + 21.25°C = 71.25°C
The maximum junction temperature must not exceed
the specified 125°C for safe continuous regulator op-
eration.
Thermal Limiting
The thermal shutdown temperature of the LT1573 is
approximately 150°C. The thermal limit of the LT1573 can
be used to protect both the LT1573 and the external PNP
pass transistor. This is accomplished by thermally cou-
pling the LT1573 to the PNP power transistor by locating
the LT1573 as close to the PNP transistor as possible. In
this case, the power dissipation of the power transistor
must be considered in the LT1573 maximum junction
temperature calculation.
Compensation
In order to improve the transient response to regulator
output load variation, a capacitor in series with a resistor
can be inserted between the VOUT and COMP pins. For the
microprocessor power supply regulator system based on
the LT1573 and the PNP transistor D45H11 with 24 1µF
surface mount ceramic capacitors in parallel with one
220µF surface mount tantalum capacitor at the output as
shown in Figure 1, a 100pF capacitor in series with a 1k
resistor is recommended. In theory, the output capacitor
forms the dominant pole of the regulator system. An
internal compensation capacitor forms another pole. The
external compensation capacitor and resistor form a zero
which adds phase margin to the regulator system to
prevent high frequency oscillation. The LT1573 has an
internal pole at approximately 5kHz. An external compen-
sation zero between 10kHz and 100kHz is usually required
to stabilize the regulator. The zero frequency is primarily
determined by the compensation capacitor and can be
roughly calculated by the following equation:
30 pF
( ) ( ( ) )fZERO = 40kHz CCOMP pF ,10 ≤ CCOMP ≤ 100
A compensation resistor between 1k and 10k is sug-
gested. A compensation resistor of 5k works for most
cases. In some cases, a greater compensation resistor is
needed to stop oscillation above 1MHz. In some cases, the
output capacitor may have enough equivalent series resis-
tance (ESR) to generate the required zero and the external
compensation zero may not be needed.
Output Capacitor
The LT1573 is designed to be used with an external PNP
transistor with a high gain-bandwidth product fT to make
a regulator with a very fast transient response, which can
minimize the size of the output capacitor. For a regulator
made of an LT1573 and a D45H11, only one 10µF surface
mount ceramic capacitor at the output is enough for the
regulator to handle the output load varying up to 5A in a
few hundred nanoseconds interval and to remain stable
with a 30pF capacitor in series with a 7.5k resistor between
the VOUT and COMP pins. If tighter voltage regulation is
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LT1573CS8.PDF ] | |
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