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PDF LTC1417C Data sheet ( Hoja de datos )
| Número de pieza | LTC1417C | |
| Descripción | Low Power 14-Bit/ 400ksps Sampling ADC Converter with Serial I/O | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s 16-Pin Narrow SSOP Package (SO-8 Footprint)
s Sample Rate: 400ksps
s ±1.25LSB INL and ±1LSB DNL Max
s Power Dissipation: 20mW (Typ)
s Single Supply 5V or ±5V Operation
s Serial Data Output
s No Missing Codes Over Temperature
s Power Shutdown: Nap and Sleep
s External or Internal Reference
s Differential High Impedance Analog Input
s Input Range: 0V to 4.096V or ±2.048V
s 81dB S/(N + D) and – 95dB THD at Nyquist
U
APPLICATIO S
s High Speed Data Acquisition
s Digital Signal Processing
s Isolated Data Acquisition Systems
s Audio and Telecom Processing
s Spectrum Instrumentation
LTC1417
Low Power 14-Bit, 400ksps
Sampling ADC Converter
with Serial I/O
DESCRIPTIO
The LTC®1417 is a low power, 400ksps, 14-bit A/D con-
verter. This versatile device can operate from a single 5V or
±5V supplies. An onboard high performance sample-and-
hold, a precision reference and internal trimming minimize
external circuitry requirements. The low 20mW power
dissipation is made even more attractive with two user-
selectable power shutdown modes.
The LTC1417 converts 0V to 4.096V unipolar inputs when
using a 5V supply and ±2.048V bipolar inputs when using
±5V supplies. DC specs include ±1.25LSB INL, ±1LSB
DNL and no missing codes over temperature. Outstanding
AC performance includes 81dB S/(N + D) and 95dB THD
at a Nyquist input frequency of 200kHz.
The internal clock is trimmed for 2µs maximum conver-
sion time. A separate convert start input and a data ready
signal (BUSY) ease connections to FIFOs, DSPs and
microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
EQUIVALE T BLOCK DIAGRA
A 400kHz, 14-Bit Sampling A/D Converter in a Narrow 16-Lead SSOP Package
LTC1417
1
AIN+
S/H
AIN– 2
5V
10µF
16 VDD
14-BIT ADC
14
REFCOMP
10µF
4
4.096V
BUFFER
SERIAL
PORT
VREF
1µF
3
8k 2.5V
REFERENCE
TIMING AND
LOGIC
5 AGND
15 VSS
10 DGND
(0V OR – 5V)
6
EXTCLKIN
7 SCLK
8
CLKOUT
9
DOUT
14 BUSY
12 RD
13 CONVST
11 SHDN
1417 TA01
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
14 86
80
12 74
68
10 62
8
6
4
2
1k 10k 100k 1M
INPUT FREQUENCY (Hz)
1417 TA02
1
1 page  
LTC1417
WU
TI I G CHARACTERISTICS The q indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
tH SCLK
tL SCLK
tH EXTCLKIN
tL EXTCLKIN
SCLK High Time
SCLK Low Time
EXTCLKIN High Time
EXTCLKIN Low Time
(Note 9)
(Note 9)
q 10
q 10
q 0.04
q 0.04
ns
ns
20 µs
20 µs
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA without latchup if the pin is driven below VSS (ground
for unipolar mode) or above VDD.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended AIN+ input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 625ns after
conversion start or after BUSY rises.
Note 12: Typical RMS noise at the code transitions. See Figure 2 for
histogram.
Note 13: t11 of 40ns maximum allows fSCLK up to 10MHz for rising
capture with 50% duty cycle. fSCLK up to 20MHz for falling capture with
5ns setup time.
TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C)
Typical INL Curve
1.0
0.5
Differential Nonlinearity
vs Output Code
1.0
0.5
00
–0.5 – 0.5
–1.0
0
4096
8192
12288
OUTPUT CODE
16384
1417 G01
– 1.0
0
4096
8192 12288
OUTPUT CODE
16384
1417 G02
S/(N + D) vs Input Frequency
and Amplitude
90
80 VIN = 0dB
70
60 VIN = –20dB
50
40
30 VIN = –60dB
20
10
0
1k 10k 100k 1M
INPUT FREQUENCY (Hz)
1417 G03
5
5 Page 
LTC1417
APPLICATIONS INFORMATION
0
– 20
– 40
– 60
– 80
–100
–120
1
THD
3RD
2ND
10 100
INPUT FREQUENCY (kHz)
1000
1417 G05
Figure 5. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, 2nd order IMD terms include (fa ± fb). If
the two input sine waves are equal in magnitude, the value
(in decibels) of the 2nd-order IMD products can be
expressed by the following formula:
0 fSAMPLE = 400kHz
fIN1 = 97.303466kHz
– 20 fIN2 = 104.632568kHz
VIN = 4.096VP-P
– 40
– 60
– 80
– 100
– 120
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
1417 G09
Figure 6. Intermodulation Distortion Plot
( ) ( )Amplitude at fa ± fb
IMD fa + fb = 20Log
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is the input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB from a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1417 has been designed to optimize input band-
width, allowing the ADC to undersample input signals with
frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1417 are easy to
drive. The inputs may be driven differentially or as a single-
ended input (i.e., the AIN– input is grounded). The AIN+ and
AIN– inputs are sampled at the same instant. Any
unwanted signal that is common to both inputs will be
reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1417
inputs can be driven directly. As source impedance
increases, so will acquisition time (see Figure 7). For
minimum acquisition time, with high source impedance, a
buffer amplifier must be used. The only requirement is that
the amplifier driving the analog input(s) must settle after
the small current spike before the next conversion starts —
500ns for full throughput rate.
11
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| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet LTC1417C.PDF ] | |
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