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PDF CXD2510Q Data sheet ( Hoja de datos )
| Número de pieza | CXD2510Q | |
| Descripción | CD Digital Signal Processor | |
| Fabricantes | Sony | |
| Logotipo |  |
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CD Digital Signal Processor
CXD2510Q
Description
The CXD2510Q is a digital signal processor LSI for
CD players and is equipped with the following functions.
• Wide frame jitter margin (±28 frames) due to a built-
in 32K RAM
• Bit clock, which strobes the EFM signal, is
generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
• Quadruple-speed, double-speed and variable pitch
playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error
correction
• Digital spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• Serial bus-based CPU interface
• Error correction monitor signals are output from a
new CPU interface.
• Servo auto sequencer
• Fine search which performs high-precision track
jumps
• Digital audio interface output
• Digital level meter, peak meter
• Bilingual compatible
Features
• All digital signals processed with a single chip
during playback
• High-integrated mounting possible due to a built-in
RAM
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
VDD
–0.3 to +7.0 V
• Input voltage
VI
–0.3 to +7.0 V
(VSS – 0.3V to VDD + 0.3V)
• Output voltage
VO
–0.3 to +7.0 V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference
Vss – AVss –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
80 pin QFP (Plastic)
-L01
-L051
Recommended Operating Conditions
• Supply voltage
VDD∗ 4.50 to 5.50 V
• Operating temperature Topr –20 to +75 °C
∗ The VDD (min.) for the CXD2510Q varies according
to the playback speed and built-in VCO selection.
The VDD (min.) is 4.50 V when high speed VCO
and quadruple-speed playback are selected
(variable pitch off). The VDD (min.) for the
CXD2510Q under various conditions are as shown
in the following table.
Playback
VDD (min.) [V]
speed VCO high-speed VCO normal-speed
×4
× 2∗1
4.50
4.00
—
—
× 2 3.40
4.00
×1
× 1∗2
3.40
3.40
3.40
3.40
Dashes indicate that there is no assurance of the
processor operating. All values are for variable pitch off.
∗1 When the internal operation of the LSI is set to
normal-speed playback and the operating clock
of the signal processor is doubled, double-speed
playback results.
∗2 When the internal operation of the LSI is set to
double-speed mode and the crystal oscillating
frequency is halved in low power consumption
mode, normal-speed playback results.
Input/output Capacitances
• Input capacitance CI
• Output capacitance CO
Note) Measurement conditions
12 (max.)
pF
12 (max.)
pF
for high impedance
VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94412A11
1 page  
CXD2510Q
Pin
No.
Symbol
I/O
Description
66 SQSO O 1, 0 Sub Q 80-bit and PCM peak and level data 16-bit output.
67 SQCK I
SQSO readout clock input.
68 MUTE I
High: mute; low: release
69 SENS — 1, Z, 0 SENS output to CPU.
70 XRST I
System reset. Reset when low.
71 DATA I
Serial data input from CPU.
72 XLAT I
Latch input from CPU. Serial data is latched at the falling edge.
73 VDD
Power supply (5V).
74 CLOK I
Serial data transfer clock input from CPU.
75 SEIN I
SENS input from SSP.
76 CNIN I
Track jump count signal input.
77 DATO O 1, 0 Serial data output to SSP.
78 XLTO O 1, 0 Serial data latch output to SSP. Latched at the falling edge.
79 CLKO O 1, 0 Serial data transfer clock output to SSP.
80 MIRR I
Mirror signal input.
Notes)
• The 64-bit slot is an LSB first, two's complement output, and the 48-bit slot is an MSB first, two's complement
output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
• XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal
transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µ.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
–5–
5 Page 
CXD2510Q
The meaning of the data for each address is explained below.
$4X commands
Register name
Data 1
Data 2
Data 3
Command
MAX timer value
Timer range
4
AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0
0
0
Command
AS3
AS2
AS1
AS0
Cancel
0000
FineSearch
0 1 0 RXF
Focus-On
0111
1 TrackJump
1 0 0 RXF
10 TrackJump 1 0 1 RXF
2N TrackJump 1 1 0 RXF
RXF = 0 Forward
RXF = 1 Reverse
• When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the TRACK JUMP commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto
sequence is interrupted.
MT3
Max. timer value
MT2
MT1
MT0
LSSL
Timer range
00
0
23.2ms
11.6ms
5.8ms
2.9ms
0
0
0
0
1.49s
0.74s
0.37s
0.18s
1
0
0
0
• To invalidate the MAX timer, set the MAX timer value to 0.
$5X commands
Timer
Blind (A, E), Overflow (C, G)
Brake (B)
TR3
0.18ms
0.36ms
TR2
0.09ms
0.18ms
TR1
0.045ms
0.09ms
TR0
0.022ms
0.045ms
$6X commands
Register name
Data 1
Data 2
KICK (D)
KICK (F)
6
SD3 SD2 SD1 SD0 KF3 KF2 KF1 KF0
Timer
When executing KICK (D) $44 or $45
When executing KICK (D) $4C or $4D
SD3
23.2ms
11.6ms
SD2
11.6ms
5.8ms
SD1
5.8ms
2.9ms
SD0
2.9ms
1.45ms
KICK (F)
Timer
KF3
0.72ms
KF2
0.36ms
– 11 –
KF1
0.18ms
KF0
0.09ms
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD2510Q.PDF ] | |
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