PDF PI49FCT3805D Data sheet ( Hoja de datos )

Número de pieza	PI49FCT3805D
Descripción	3.3V/ 2 x 1:5 CMOS Clock Driver
Fabricantes	ETC
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No Preview Available ! PI49FCT3805D1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 3.3V, 2 x 1:5 CMOS Clock Driver Features Low output skew: <270ps Switching frequency of 133 MHz Fast output rise/fall time: <1.5ns Low propagation delay: <3.0ns Low input capacitance: <6.0pF Balanced CMOS outputs Industrial Temperature: 40°C to +85°C 3.3V ±10% operation Packages available: 20-pin 300-mil wide SOIC (S) 20-pin 150-mil wide QSOP (Q) 20-pin 209-mil wide SSOP (H) Logic Block Diagram OEA INA 5 OA0–4 INB OEB 5 OB0–4 MON Description Pericom Semiconductors PI49FCT series of logic circuits are produced using the Companys advanced submicron CMOS technology to achieve fast speed, low skew, fast slew rate, and low propagation delay for most computing and communication applications. The PI49FCT3805D is composed of non-inverting drivers. The outputs are configured into 2 groups of one-in, five-out with independent output enable. Group B has an extra MON output. Excellent output signals to power and ground ratio minimize power and ground noise and also improves output performance. Pin Configuration VCC OA0 OA1 OA2 GNDA OA3 OA4 GNDQ OEA INA 1 20 2 19 3 18 4 17 20-Pin 5 H,Q,S 16 6 15 7 14 8 13 9 12 10 11 VCCB OB0 OB1 OB2 GNDB OB3 OB4 MON OEB INB Product Pin Description Pin Name Description OEA, OEB Hi-Z State Output Enable Inputs (Active LOW) INA, INB Clock Inputs OAN, OBN Clock Outputs MON Monitor Output GND Ground VCC Power Truth Table(1) Inputs OEA, OEB INA, INB LL LH HL HH Note: 1. H = High Voltage Level L = Low Voltage Level Z = High Impedance Outputs OAN, OBN MON LL HH ZL ZH 1 PS8492 08/10/00 1 page PI49FCT3805D 112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122311.2233344V5566,772889900x1122133:445556677C8899M001122O3344S556677C8899l00o11c2211k2233D4455r6677i88v99e0011r22 Switching Waveforms Propagation Delay Input Output tPLH Enable and Disable Times 3V 1.5V tPHL 0V VOH 1.5V VOL Output Skew tSK(o) Input tPLHx Ox tSK(o) Oy tPLHy 3V 1.5V tPHLx 0V VOH 1.5V VOL tSK(o) VOH 1.5V VOL tPHLy Enable OE Disable tPZL Output Normally Low Switch Closed tPZH Output Normally High Switch Open tPLZ 3.0V 1.5V tPHZ 1.5V 0V 3V 1.5V 0V 3.0V 0.3V VOL 0.3V VOH 0V Package Skew tSK(t) Input tPLH1 Package 1 Output Package 2 Output tSK(t) tPLH2 3V 1.5V tPHL1 0V VOH 1.5V VOL tSK(t) VOH 1.5V VOL tPHL2 tSK(o) = \| tPLHy – tPLHx \| or \| tPHLy – tPHLx \| Pulse Skew tSK(p) Input tPLH Output tPHL tSK(p) = \| tPHL – tPLH \| 3V 1.5V 0V VOH 1.5V VOL tSK(t) = \| tPLH2 – tPLH1 \| or \| tPHL2 – tPHL1 \| 5 PS8492 08/10/00 5 Page

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