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Número de pieza | PHP11N06LT | |
Descripción | N-channel TrenchMOS transistor Logic level FET | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PHP11N06LT (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
No Preview Available ! Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP11N06LT, PHB11N06LT
PHD11N06LT
FEATURES
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 55 V
ID = 10.5 A
RDS(ON) ≤ 150 mΩ (VGS = 5 V)
RDS(ON) ≤ 130 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PHP11N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB11N06LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD11N06LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
SOT428 (DPAK)
tab
2 drain 1
3 source
tab drain
1 23
2
13
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
Tj ≤ 150˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
± 15
± 20
10.3
7.3
41
33
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
August 1999
1
Rev 1.000
1 page Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP11N06LT, PHB11N06LT
PHD11N06LT
Drain current, ID (A)
10
9 VDS > ID X RDS(ON)
8
7
6
5
4
3
2 175 C
1 Tj = 25 C
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
5
Transconductance, gfs (S)
8
VDS > ID X RDS(ON)
7
Tj = 25 C
6
5 175 C
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Normalised On-state Resistance
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Threshold Voltage, VGS(TO) (V)
2.25
2 maximum
1.75
1.5 typical
1.25
1 minimum
0.75
0.5
0.25
0
-60 -40 -20
0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
1.0E-01 Drain current, ID (A)
1.0E-02
1.0E-03
1.0E-04
1.0E-05
minimum
typical
maximum
1.0E-06
0
0.5 1 1.5 2
Gate-source voltage, VGS (V)
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Capacitances, Ciss, Coss, Crss (pF)
1000
Ciss
100
Coss
Crss
10
0.1
1 10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
5
Rev 1.000
5 Page Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
MOUNTING INSTRUCTIONS
Dimensions in mm
Product specification
PHP11N06LT, PHB11N06LT
PHD11N06LT
7.0
7.0
2.15 1.5
2.5
4.57
Fig.20. SOT428 : soldering pattern for surface mounting.
August 1999
11
Rev 1.000
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet PHP11N06LT.PDF ] |
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