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PDF PHB80N06LT Data sheet ( Hoja de datos )
| Número de pieza | PHB80N06LT | |
| Descripción | TrenchMOS transistor Logic level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHB80N06LT
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using ’trench’ technology
the device features very low on-state
resistance and has integral zener
diodes giving ESD protection up to
2kV. It is intended for use in DC-DC
converters and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)1
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
MAX.
55
75
178
175
14
PINNING - SOT404
PIN DESCRIPTION
1 gate
2 drain
3 source
mb drain
PIN CONFIGURATION
mb
2
13
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)1
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
RGS = 20 kΩ
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
VC
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
75
56
240
178
175
UNIT
V
V
V
A
A
A
W
˚C
MIN.
-
MAX.
2
UNIT
kV
1 Current limited by package to 75A from a theoretical value of 80A.
December 1997
1
Rev 1.100
1 page  
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHB80N06LT
100
ID/A
80
60
40
20
Tj/C = 175
25
0
0 1 2 VGS/V 3 4 5
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
70
gfs/S
60
50
40
30
20
10
0
0 20 40 ID/A 60 80 100
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2.5 a
BUK959-60 Rds(on) normlised to 25degC
2
1.5
1
0.5
-100
-50
0 50 100 150 200
Tmb / degC
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK959-60
0.5
0
-100
-50
0 50
Tj / C
100 150 200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ 98%
1E-04
1E-05
1E-05
0 0.5 1 1.5 2 2.5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
3
6
5
4
3 Ciss
2
1
0
0.01 0.1
1 VDS/V 10
Coss
Crss
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
December 1997
5
Rev 1.100
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PHB80N06LT.PDF ] | |
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