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Número de pieza | PHB108NQ03LT | |
Descripción | TrenchMOS logic level FET | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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No Preview Available ! PHP/PHB/PHD108NQ03LT
TrenchMOS™ logic level FET
Rev. 02 — 11 September 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP108NQ03LT in SOT78 (TO-220AB)
PHB108NQ03LT in SOT404 (D2-PAK)
PHD108NQ03LT in SOT428 (D-PAK).
1.2 Features
s Logic level compatible
s Very low on-state resistance
1.3 Applications
s DC to DC converters
s Switched mode power supplies
1.4 Quick reference data
s VDS = 25 V
s Ptot = 180 W
s ID = 75 A
s RDSon ≤ 6 mΩ
2. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT428, simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d) [1] mb
mb
mb
3 source (s)
mb mounting base,
connected to
drain (d)
MBK106
123
2
1 3 MBK116
2
1
Top view
3
MBK091
SOT78 (TO-220AB) SOT404 (D2-PAK) SOT428 (D-PAK)
Symbol
g
MBB076
[1] It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
d
s
1 page Philips Semiconductors
PHP/PHB/PHD108NQ03LT
TrenchMOS™ logic level FET
5. Characteristics
Table 4: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
VGS(th) gate-source threshold voltage
ID = 1 mA; VDS = VGS; Figure 9
IDSS drain-source leakage current
IGSS gate-source leakage current
VDS = 25 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±10 V; VDS = 0 V
RDSon drain-source on-state resistance
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
Tj = 175 °C
VGS = 10 V; ID = 25 A
Dynamic characteristics
Qg(tot) total gate charge
ID = 40 A; VDD = 15 V; VGS = 5 V; Figure 13
Qgs gate-source charge
Qgd gate-drain (Miller) charge
Ciss input capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11
Coss output capacitance
Crss
td(on)
tr
reverse transfer capacitance
turn-on delay time
rise time
VDD = 15 V; RD = 0.6 Ω; VGS = 5 V; RG = 10 Ω
td(off)
turn-off delay time
tf fall time
Source-drain diode
VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
trr reverse recovery time
Qr recovered charge
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V;
VDS = 25 V
Min Typ Max Unit
25 -
22 -
1-
-V
-V
2V
- 0.05 1 µA
- - 500 µA
- 0.02 100 nA
- 6.2 7.5 mΩ
- 10 14 mΩ
- 5.1 6.0 mΩ
- 23 - nC
- 8.4 - nC
- 7.3 9.9 nC
- 1990 - pF
- 580 - pF
- 230 - pF
- 24 - ns
- 102 - ns
- 53 - ns
- 54 - ns
- 0.9 1.2 V
- 34 - ns
- 27 - nC
9397 750 10159
Product data
Rev. 02 — 11 September 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5 of 14
5 Page Philips Semiconductors
PHP/PHB/PHD108NQ03LT
TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
EA
A2
b2 A1
mounting
base
D
HE
L2
2
1
L
3
b1
e
b wM A
e1
L1
c
D1
E1
0 10 20 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A1(1) A2 b
b1 b2
c
mm 2.38 0.65 0.93 0.89 1.1 5.46 0.4
2.22 0.45 0.73 0.71 0.9 5.26 0.2
D
6.22
5.98
D1 E
min.
4.0 6.73
6.47
E1 e e1 HE L
4.81 2.285 4.57 10.4 2.95
4.45 9.6 2.55
L1
min.
0.5
L2
0.9
0.5
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT428
TO-252
SC-63
w
y
max.
0.2 0.2
ISSUE DATE
99-09-13
01-12-11
Fig 16. SOT428 (D-PAK).
9397 750 10159
Product data
Rev. 02 — 11 September 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
11 of 14
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Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet PHB108NQ03LT.PDF ] |
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