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PDF LMX2330 Data sheet ( Hoja de datos )
| Número de pieza | LMX2330 | |
| Descripción | PLLatinum Dual Frequency Synthesizer for RF Personal Communications | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 1999
LMX2330A/LMX2331A/LMX2332A
PLLatinum™ Dual Frequency Synthesizer for RF
Personal Communications
LMX2330A 2.5 GHz/510 MHz
LMX2331A 2.0 GHz/510 MHz
LMX2332A 1.2 GHz/510 MHz
General Description
The LMX233xA family of monolithic, integrated dual fre-
quency synthesizers, including prescalers, is to be used as a
local oscillator for RF and first IF of a dual conversion trans-
ceiver. It is fabricated using National’s ABiC IV silicon
BiCMOS process.
The LMX233xA contains dual modulus prescalers. A 64/65
or a 128/129 prescaler (32/33 or 64/65 in the 2.5 GHz
LMX2330A) can be selected for the RF synthesizer and a
8/9 or a 16/17 prescaler can be selected for the IF synthe-
sizer. LMX233XA, which employs a digital phase locked loop
technique, combined with a high quality reference oscillator
and loop filters, provides the tuning voltages for voltage con-
trolled oscillators to generate very stable low noise RF and
IF local oscillator signals. Serial data is transferred into the
LMX233xA via a three wire interface (Data, Enable, Clock).
Supply voltage can range from 2.7V to 5.5V. The LMX233xA
family features very low current consumption;
LMX2330A — 13 mA at 3V, LMX2331A — 12 mA at 3V,
LMX2332A — 8 mA at 3V.
The LMX233xA are available in a TSSOP 20-pin surface
mount plastic package.
Features
n 2.7V to 5.5V operation
n Low current consumption
n Selectable powerdown mode: ICC = 1 µA typical at 3V
n Dual modulus prescaler:
LMX2330A (RF) 32/33 or 64/65
LMX2331A/32A (RF) 64/65 or 128/129
LMX2330A/31A/32A (IF) 8/9 or 16/17
n Selectable charge pump TRI-STATE® mode
n Selectable FastLock™ mode
n Small outline, plastic, surface mount TSSOP 0.173"
wide package
Applications
n Portable Wireless Communications (PCS/PCN, cordless)
n Cordless and cellular telephone systems
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
n Other wireless communication systems
Functional Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
Fastlock™, MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012331
DS012331-1
www.national.com
1 page  
Charge Pump Characteristics
VCC = 3.0V, VP = 3.0V; −40˚C < TA < 85˚C, except as specified
Symbol
Parameter
Conditions
IDo-SOURCE
IDo-SINK
IDo-SOURCE
IDo-SINK
IDo-TRI
IDo-SINK vs
IDo-SOURCE
IDo vs VDo
Charge Pump Output Current
Charge Pump TRI-STATE
Current
CP Sink vs
Source Mismatch (Note 4)
CP Current vs Voltage
(Note 3)
VDo = VP/2, ICPo = HIGH**
VDo = VP/2, ICPo = HIGH**
VDo = VP/2, ICPo = LOW**
VDo = VP/2, ICPo = LOW**
0.5V ≤ VDo ≤ VP − 0.5V
−40˚c < TA < 85˚C
VDo = VP/2
TA = 25˚C
0.5V ≤ VDo ≤ VP − 0.5V
TA = 25˚C
IDo vs TA
CP Current vs Temperature
(Note 5)
VDo = VP/2
−40˚C < TA < 85˚C
** See PROGRAMMABLE MODES for ICPo description.
Note 3: See charge pump current specification definitions below.
Note 4: See charge pump current specification definitions below.
Note 5: See charge pump current specification definitions below.
Value
Units
Min Typ Max
−4.5
mA
4.5 mA
−1.125
mA
1.125
mA
−2.5
2.5 nA
3 10 %
10 15 %
10 %
5 www.national.com
5 Page 
Functional Description (Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care
bits.
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
RF
Divide
NNNNNNN
Ratio
7654321
A
0 0000000
1 0000001
• •••••••
127 1 1 1 1 1 1 1
Note: Divide ratio: 0 to 127
B≥A
IF
DS012331-15
Divide
NNNNNNN
Ratio
7654321
A
0 XXX 0 0 0 0
1 XXX 0 0 0 1
• •••••••
15 X X X 1 1 1 1
X = DON’T CARE condition
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide
Ratio
B
3
4
•
2047
NNNNNNNNN
18 17 16 15 14 13 12 11 10
000000000
000000001
•••••••••
111111111
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B≥A
N
9
1
0
•
1
N
8
1
0
•
1
PULSE SWALLOW FUNCTION
fVCO = [(P x B) + A] x fOSC/R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter
(0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF}, A ≤ B)
fOSC: Output frequency of the external reference frequency oscillator
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual moduIus prescaler (for IF ; P = 8 or 16;
for RF ; LMX2330A: P = 32 or 64 LMX2331A/32A: P = 64 or 128)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump
TRI-STATE and the output of the FoLD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The pro-
grammable modes are shown in Table 1. Truth table for the programmable modes and FoLD output are shown in Table 2 and
Table 3.
11 www.national.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet LMX2330.PDF ] | |
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