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PDF LMV822 Data sheet ( Hoja de datos )
| Número de pieza | LMV822 | |
| Descripción | Low Voltage / Low Power / R-to-R Output / 5 MHz Op Amps | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LMV822 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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August 1999
LMV821 Single/ LMV822 Dual/ LMV824 Quad
Low Voltage, Low Power, R-to-R Output, 5 MHz Op Amps
General Description
The LMV821/LMV822/LMV824 bring performance and
economy to low voltage / low power systems. With a 5 MHz
unity-gain frequency and a guaranteed 1.4 V/µs slew rate,
the quiescent current is only 220 µA/amplifier (2.7 V). They
provide rail-to-rail (R-to-R) output swing into heavy loads
(600 Ω Guarantees). The input common-mode voltage range
includes ground, and the maximum input offset voltage is
3.5mV (Guaranteed). They are also capable of comfortably
driving large capacitive loads (refer to the application notes
section).
The LMV821 (single) is available in the ultra tiny SC70-5
package, which is about half the size of the previous title
holder, the SOT23-5.
Overall, the LMV821/LMV822/LMV824 (Single/Dual/Quad)
are low voltage, low power, performance op amps, that can
be designed into a wide range of applications, at an eco-
nomical price.
Features
(For Typical, 5 V Supply Values; Unless Otherwise Noted)
n Ultra Tiny, SC70-5 Package
2.0 x 2.0 x 1.0 mm
n Guaranteed 2.5 V, 2.7 V and 5 V Performance
n Maximum VOS
3.5 mV (Guaranteed)
n VOS Temp. Drift
1 uV/˚ C
n GBW product @ 2.7 V
5 MHz
n ISupply @ 2.7 V
220 µA/Amplifier
n Minimum SR
1.4 V/us (Guaranteed)
n CMRR
90 dB
n PSRR
85 dB
n Rail-to-Rail (R-to-R) Output Swing
— @600 Ω Load
160 mV from rail
— @10 kΩ Load
55 mV from rail
n VCM @ 5 V
-0.3 V to 4.3 V
n Stable with High Capacitive Loads (Refer to Application
Section)
Applications
n Cordless Phones
n Cellular Phones
n Laptops
n PDAs
n PCMCIA
Connection Diagrams
5-Pin SC70-5/SOT23-5
14-Pin SO/TSSOP
DS100128-84
Top View
8-Pin SO/MSOP
DS100128-85
Top View
DS100128-63
Top View
© 1999 National Semiconductor Corporation DS100128
www.national.com
1 page  
2.7V AC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 2.7V, V − = 0V, VCM = 1.0V, VO = 1.35V and R L > 1 MΩ.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
in Input-Referred Current Noise
Conditions
f = 1 kHz
Typ
(Note 5)
0.1
LMV821/822/824 Limit
(Note 6)
Units
THD
Total Harmonic Distortion
f = 1 kHz, AV = −2,
RL = 10 kΩ, VO = 4.1 VPP
0.01
%
5V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 5V, V − = 0V, VCM = 2.0V, VO = 2.5V and R L > 1 MΩ.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Typ
(Note 5)
LMV821/822/824
Limit (Note 6)
Units
VOS Input Offset Voltage
1 3.5 mV
4.0 max
TCVOS
Input Offset Voltage Average
Drift
1 µV/˚C
IB Input Bias Current
40 100 nA
150 max
IOS Input Offset Current
0.5 30 nA
50 max
CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 4.0V
+PSRR
−PSRR
Positive Power Supply
Rejection Ratio
Negative Power Supply
Rejection Ratio
1.7V ≤ V+ ≤ 4V, V- = 1V, VO =
0V, VCM = 0V
-1.0V ≤ V- ≤ -3.3V, V+ =1.7V,
VO = 0V, VCM = 0V
90
85
85
72 dB
70 min
75 dB
70 min
73 dB
70 min
VCM Input Common-Mode Voltage For CMRR ≥ 50dB
Range
-0.3 -0.2 V
max
4.3 4.2 V
min
AV
Large Signal Voltage Gain
Sourcing, RL=600Ω to 2.5V,
105
VO=2.5 to 4.5V
95 dB
90 min
Sinking, RL=600Ω to 2.5V,
VO=2.5 to 0.5V
105
95 dB
90 min
Sourcing, RL=2kΩ to 2.5V,
VO=2.5 to 4.5V
105
95 dB
90 min
V O Output Swing
Sinking, RL=2kΩ to 2.5,
VO=2.5 to 0.5V
V+=5V,RL= 600Ω to 2.5V
105
4.84
95 dB
90 min
4.75 V
4.70
min
0.17 0.250 V
V+=5V, RL=2kΩ to 2.5V
4.90
.30
4.85
4.80
max
V
min
0.10
0.15
V
0.20
max
5 www.national.com
5 Page 
APPLICATION NOTE
This application note is divided into two sections: design
considerations and Application Circuits.
1.0 Design Considerations
This section covers the following design considerations:
1. Frequency and Phase Response Considerations
2. Unity-Gain Pulse Response Considerations
3. Input Bias Current Considerations
1.1 Frequency and Phase Response Considerations
The relationship between open-loop frequency response
and open-loop phase response determines the closed-loop
stability performance (negative feedback). The open-loop
phase response causes the feedback signal to shift towards
becoming positive feedback, thus becoming unstable. The
further the output phase angle is from the input phase angle,
the more stable the negative feedback will operate. Phase
Margin (φm) specifies this output-to-input phase relationship
at the unity-gain crossover point. Zero degrees of phase-
margin means that the input and output are completely in
phase with each other and will sustain oscillation at the unity-
gain frequency.
The AC tables show φm for a no load condition. But φm
changes with load. The Gain and Phase margin vs Fre-
quency plots in the curve section can be used to graphically
determine the φm for various loaded conditions. To do this,
examine the phase angle portion of the plot, find the phase
margin point at the unity-gain frequency, and determine how
far this point is from zero degree of phase-margin. The larger
the phase-margin, the more stable the circuit operation.
The bandwidth is also affected by load. The graphs of Figure
1 and Figure 2 provide a quick look at how various loads af-
fect the φm and the bandwidth of the LMV821/822/824 family.
These graphs show capacitive loads reducing both φm and
bandwidth, while resistive loads reduce the bandwidth but in-
crease the φm. Notice how a 600Ω resistor can be added in
parallel with 220 picofarads capacitance, to increase the φm
20˚(approx.), but at the price of about a 100 kHz of band-
width.
Overall, the LMV821/822/824 family provides good stability
for loaded condition.
DS100128-61
FIGURE 2. Unity-Gain Frequency vs Common Mode
Voltage for Various Loads
1.2 Unity Gain Pulse Response Considerations
A pull-up resistor is well suited for increasing unity-gain,
pulse response stability. For example, a 600 Ω pull-up resis-
tor reduces the overshoot voltage by about 50%, when driv-
ing a 220 pF load. Figure 3 shows how to implement the
pull-up resistor for more pulse response stability.
DS100128-41
FIGURE 3. Using a Pull-up Resistor at the Output for
Stabilizing Capacitive Loads
Higher capacitances can be driven by decreasing the value
of the pull-up resistor, but its value shouldn’t be reduced be-
yond the sinking capability of the part. An alternate approach
is to use an isolation resistor as illustrated in Figure 4 .
Figure 5 shows the resulting pulse response from a LMV824,
while driving a 10,000pF load through a 20 Ω isolation
resistor.
DS100128-60
FIGURE 1. Phase Margin vs Common Mode Voltage for
Various Loads
DS100128-43
FIGURE 4. Using an Isolation Resistor to Drive Heavy
Capacitive Loads
11 www.national.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LMV822.PDF ] | |
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