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PDF DSP96002RC40 Data sheet ( Hoja de datos )
| Número de pieza | DSP96002RC40 | |
| Descripción | 32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSOR | |
| Fabricantes | Motorola Inc | |
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MOTOROLA Freescale Semiconductor, Inc. Order this document by:
SEMICONDUCTOR TECHNICAL DATA
DSP96002/D, Rev. 2
DSP96002
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT
PROCESSOR
The DSP96002 is designed to support intensive graphic image and numeric processing. It is
a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024
words of data RAM (equally divided into X data and Y data memory), 1024 words of full-
speed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA)
controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE™) debug
circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units
operating in parallel. The DSP96002 has two identical memory expansion ports with control
lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and
Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which
facilitates easy interface with other processors for multiprocessor applications. Linear arrays
of DSP96002s can be implemented without glue logic. The MPU-style programming model
and instruction set allow straightforward generation of efficient, compact code. The high
speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive
applications that require floating-point processing and access to large memory subsystems.
Control Bus
18 Control
Address
32 External
Address
Switch
4
32-bit
Host
Interface
Timer
32
Data
External
Data
Bus
Switch
Address
Generation
Unit (AGU)
Dual Channel
DMA
Controller
Internal
Switch And Bit
Manipulation
Unit
YAB*
XAB*
PAB*
Program *
Memory
1024 × 32
RAM and
64 × 32
Bootstrap
ROM
Instruction
Cache
X Data *
Memory
512 × 32
RAM
512 × 32†
ROM
Y Data *
Memory
512 × 32
RAM
512 × 32†
ROM
DDB
YDB
XDB
PDB
GDB
Bus Control
Control 18
External
Address
Address
32
Switch
4
32-bit
Host
Interface
Timer
External
Data
Bus
Switch
32
Data
Clock
Generator
Program
Decode
Controller
Program
Address
Generator
Program
Interrupt
Controller
Program Controller
Data ALU
OnCE
Debug
• IEEE Floating Point Controller
• 32 × 32 Integer ALU
CLK
32-bit Buses
* Dual Access (DMA/Core)
† 1024 × 32 Virtual Locations
MODC/IRQC
MODB/IRQB
MODA/IRQA
RESET
4
Serial Debug
Port
AA0306
Figure 1 Block Diagram
©1996 MOTOROLA, INC.
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
SECTION 1
SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
The input and output signals of the DSP96002 are organized into eight functional
groups, as shown in Table 1-1 and as illustrated in Figure 1-1.
Table 1-1 DSP96002 Functional Signal Groupings
Functional Group
Power (VCCN and VCCQ)
Ground (GNDN and GNDQ)
Clock (CLK)
Interrupt and Mode Control
Port A (Address, Data, and Control)
Port B (Address, Data, and Control)
Timer/Event Counters
OnCE Port
Detailed
Description
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-6
Table 1-7
Table 1-8
Figure 1-1 is a diagram of DSP96002 signals by functional group.
MOTOROLA
DSP96002/D, Rev. 2
For More Information On This Product,
Go to: www.freescale.com
1-1
5 Page 
Freescale Semiconductor, Inc.
Signal/Connection Descriptions
Port A and Port B
Signal
Name
Type
AD0–AD31 Input/
BD0–BD31 Output
AS0–AS1
BS0–BS1
Output
AR/W
BR/W
Input
or
Output
AWR
BWR
Output
ABS Output
BBS
Table 1-6 Port A and Port B (Continued)
State
During
Reset
Signal Description
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Data Bus—D0–D31 are tri-state, active high, bidirectional
input/outputs whether the DSP is a bus master or not. The
Data Enable (DE) input acts as an output enable control for
D0–D31. As a bus master, the data lines are controlled by
the CPU instruction execution or the DMA controller. D0–
D31 are also the Host Interface data lines. If there is no
external bus activity, D0–D31 are tri-stated.
Space Select—These signals can be viewed in different
ways, depending on how the external memories are
mapped. They support splitting memory spaces among
ports, and mapping multiple memory spaces into the same
physical memory locations. S0 and S1 are outputs when the
DSP is the bus master and tri-stated when the DSP is not a
bus master. Timing is the same as the address lines A0–
A31.
Read/Write—R/W is a an output when the DSP is the bus
master and an input when not a bus master. Bus master
timing is the same as the DSP96002 address lines, giving an
“early write” signal for DRAM interfacing. R/W is high for
a read access and low for a write access. The R/W pin is
also the Host Interface read/write input. As an input, R/W
may change asynchronously relative to the input clock.
R/W goes high if the external bus is not used during an
instruction cycle.
Write Strobe —WR is an output when the DSP is the bus
master and tri-stated when it is not a bus master. WR
supports a glueless interface to external SRAMs. WR is
asserted during external memory write cycles to indicate
that the address lines A0–A32, S1, S0, BS, BL, and R/W are
stable. The output data goes to the data bus after WR is
asserted. WR requires a weak external pull-up resistor and
can be connected directly to the WE pin of a Static RAM.
Bus Strobe—BS is an output when the DSP is the bus
master and tri-stated when it is not a bus master. Bus strobe
is asserted at the start of a bus cycle (providing an “early
bus start” signal for DRAM interfacing) and deasserted at
the end of the bus cycle. The early negation provides an
“early bus end” signal useful for external bus control. If the
external bus is not used during an instruction cycle, BS
remains deasserted until the next external bus cycle.
MOTOROLA
DSP96002/D, Rev. 2
For More Information On This Product,
Go to: www.freescale.com
1-7
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