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PDF HY57V651620BLTC-10S Data sheet ( Hoja de datos )
| Número de pieza | HY57V651620BLTC-10S | |
| Descripción | 4 Banks x 1M x 16Bit Synchronous DRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY57V651620B
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
H Y 5 7 V 6 4 1 6 2 0 H G i s o f f e r i n g f u l l y s y n c h r o n o u s o p e r a t i o n r e f e r e n c e d t o a p o s i t i v e e d g e o f t h e c l o c k . A l l i n p u t s a n d o u t p u t s a r e s y nc h r o -
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
P r o g r a m m a b l e o p t i o n s i n c l u d e t h e l e n g t h o f p i p e l i n e ( R e a d l a t e n c y o f 2 o r 3 ) , t h e n u m b e r o f c o n s e c u t i v e r e a d o r w r i t e c y c l e s i n it i a t e d
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
r e a d o r w r i t e c y c l e s i n p r o g r e s s c a n b e t e r m i n a t e d b y a b u r s t t e r m i n a t e c o m m a n d o r c a n b e i n t e r r u p t e d a n d r e p l a c e d b y a n e w b u r st
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply Note)
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM or LDQM
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
ORDERING INFORMATION
Part No.
HY57V651620BTC-55
HY57V651620BTC-6
HY57V651620BTC-7
HY57V651620BTC-75
HY57V651620BTC-8
HY57V651620BTC-10P
HY57V651620BTC-10S
HY57V651620BTC-10
HY57V651620BLTC-55
HY57V651620BLTC-6
HY57V651620BLTC-7
HY57V651620BLTC-75
HY57V651620BLTC-8
HY57V651620BLTC-10P
HY57V651620BLTC-10S
HY57V651620BLTC-10
Clock Frequency
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
100MHz
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
100MHz
Power
Organization Interface
Normal
4Banks x 1Mbits
x16
LVTTL
Low power
Package
400mil 54pin TSOP II
Note : VDD(Min) of HY57V651620B(L)TC-55/6/7 is 3.135V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.9/Apr.01
1 page  
C A P A C I T A N C E ( T A= 25°C , f=1MHz)
Parameter
Input capacitance
Data input / output capacitance
Pin
CLK
A0 ~ A11, BA0, BA1, CKE, C S, RAS,
CAS, W E, UDQM, LDQM
DQ0 ~ DQ15
OUTPUT LOAD CIRCUIT
Symbol
C I1
CI 2
Min
2
2.5
C I/O
2
HY57V651620B
Max
4
5
6.5
Unit
pF
pF
pF
Output
V t t= 1 . 4 V
RT=250 Ω
Output
50pF
50 pF
DC Output Load Circuit
AC Output Load Circuit
D C C H A R A C T E R I S T I C S I (TA=0 to 70°C , VDD =3.3 ±0.3VNote3)
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Symbol
ILI
IL O
VOH
VOL
Min.
-1
-1
2.4
-
Note :
1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V
2.DOUT is disabled, V OUT=0 to 3.6
3..VDD(min) of HY57V651620B(L)TC-55/6/7 is 3.135V
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
IO H = - 4 m A
IOL = + 4 m A
Rev. 1.9/Apr.01
5
5 Page 
COMMAND TRUTH TABLE
HY57V651620B
Command
A10/
CKEn-1 CKEn
CS
RAS CAS
WE
DQM
ADDR
AP
BA
Mode Register Set
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
DQM
Auto Refresh
Self Refresh1
Entry
Exit
H
H
H
H
H
H
H
H
H
H
L
Precharge
power down
Entry
Exit
H
L
Clock
Suspend
Entry
Exit
H
L
X L LL LX
OP code
HX XX
XX
L HH H
X
X L LHHX
RA
V
L
X L H L H X CA
H
V
L
X L H L L X CA
H
V
HX
X L LH L X X
LV
X L HH L X
X
X VX
H L LLHX
X
L L LLHX
HX XX
HX
L HH H
X
HX XX
LX
L HH H
HX XX
HX
L HH H
X
HX XX
LX
L V VV
X
H XX
Note
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2 . X = D o n′t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s ,
Opcode = Operand Code, NOP = No Operation
Rev. 1.9/Apr.01
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HY57V651620BLTC-10S.PDF ] | |
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