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PDF DS92CK16 Data sheet ( Hoja de datos )
| Número de pieza | DS92CK16 | |
| Descripción | 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1999
DS92CK16
3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver
General Description
The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one
to six CMOS differential clock distribution device utilizing Bus
Low Voltage Differential Signaling (BLVDS) technology. This
clock distribution device is designed for applications requir-
ing ultra low power dissipation, low noise, and high data
rates. The BLVDS side is a transceiver with a separate chan-
nel acting as a return/source clock.
The DS92CK16 accepts BLVDS (300 mV typical) differential
input levels, and translates them to 3V CMOS output levels.
An output enable pin OE , when high, forces all CLKOUT pins
high.
The device can be used a source synchronous driver. The
selection of the source driving is controlled by the CrdCLKIN
and DE pins. This device can be the master clock, driving the
inputs of other clock I/O pins in a multipoint environment.
Easy master/slave clock selection is achieved along a back-
plane.
Features
n Master/Slave clock selection in a backplane application
n 125 MHz operation (typical)
n 100 ps duty cycle distortion (typical)
n 50 ps channel to channel skew (typical)
n 3.3V power supply design
n Glitch-free power on at CLKI/O pins
n Low Power design (20 mA @ 3.3V static)
n Accepts small swing (300 mV typical) differential signal
levels
n Industrial temperature operating range (-40˚C to +85˚C)
n Available in 24-pin TSSOP Packaging
Function Diagram and Truth Table
Receive Mode Truth Table
INPUT
OE DE CrdCLKIN (CLKI/O+)–(CLKI/O−)
HH
X
X
LH
X
VID≥ 0.07V
LH
X
VID≤ −0.07V
L = Low Logic State
H = High Logic State
X = Irrelevant
Z = TRI-STATE
OUTPUT
CLKOUT
H
H
L
DS101082-1
Driver Mode Truth Table
INPUT
OUTPUT
OE DE CrdCLKIN CLK/I/O+ CLKI/O− CLKOUT
LL
L
L HL
LL
H
H LH
HL
L
L HH
HL
H
H LH
HH
X
Z ZH
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101082
www.national.com
1 page  
Switching Characteristics (Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 7, 8).
Symbol
Parameter
Conditions
Min Typ Max Units
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLDD
Differential Propagation Delay High to Low. CrdCLKIN
to CLKI/O
tPLHDD
Differential Propagation Delay Low to High. CrdCLKIN
to CLKI/O
tPHLCrd
tPLHCrd
tSK1D
tSK2D
tTLHD
CrdCLKIN to CLKOUT Propagation Delay High to Low
CrdCLKIN to CLKOUT Propagation Delay Low to High
Duty Cycle Distortion (pulse skew)
|tPLH–tPHL| (Note 13)
Differential Part-to-Part Skew (Note 14)
Differential Transition Time (Note 9)
(20% to 80% )
CL = 15 pF
RL = 37.5Ω
Figures 6, 7
CL = 15 pF
Figures 8, 9
0.5 1.8 2.5 ns
0.5 1.8 2.5 ns
2.0 4.5 6.0 ns
2.0 4.5 6.0 ns
600 ps
2.0 ns
0.4 0.75 1.4
ns
tTHLD
Differential Transition Time (Note 9)
(80% to 20% )
0.4 0.75 1.4
ns
tPHZD
tPLZD
tPZHD
tPZLD
Transition Time High to TRI-STATE. DE to CLKI/O
Transition Time Low to TRI-STATE. DE to CLKI/O
Transition Time TRI-STATE to High. DE to CLKI/O
Transition Time TRI-STATE to Low. DE to CLKI/O
VIN = 0V to VCC
CL = 15 pF,
RL = 37.5Ω
Figures 10, 11
10 ns
10 ns
32 ns
32 ns
fMAX
Maximum Operating Frequency (Note 15)
100 125
MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. These ratings are not meant to imply that the
devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: ESD Rating: ESD qualification is performed per the following: HBM (1.5 kΩ, 100 pF), Machine Model (250V, 0Ω), IEC 1000-4-2. All VCC pins connected to-
gether, all ground pins connected together.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VID, VOD, VTH,
and VTL.
Note 4: All typicals are given for: VCC = +3.3V and TA = +25˚C.
Note 5: The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 0.2V to 2.2V A VID up to |VCC–0V| may be applied between the CLKI/O+
and CLKI/O− inputs, with the Common Mode set to VCC/2.
Note 6: Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
Note 7: CL includes probe and fixture capacitance.
Note 8: Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50Ω, tr = 1 ns, tf = 1 ns (10%–90%). To ensure fastest propagation delay and
minimum skew, clock input edge rates should not be slower than 1 ns/V; control signals not slower than 3 ns/V. In general, the faster the input edge rate, the better
the AC performance.
Note 9: All device output transition times are based on characterization measurements and are guaranteed by design.
Note 10: tSK1R is the difference in receiver propagation delay (|tPLH–tPHL|) of one device, and is the duty cycle distortion of the output at any given temperature and
VCC. The propagation delay specification is a device to device worst case over process, voltage and temperature.
Note 11: tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter
is guaranteed by design and characterization.
Note 12: tSK3R, part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction. This specification
applies to devices over recommended operating temperature and voltage ranges, and across process distribution. TSK3R is defined as Max–Min differential propa-
gation delay.This parameter is guaranteed by design and characterization.
Note 13: tSK1D is the difference in driver propagation delay (|tPLH–tPHL|) and is the duty cycle distortion of the CLKI/O outputs.
Note 14: tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This specification ap-
plies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK2D is defined as Max–Min differential propagation
delay.
Note 15: Generator input conditions: tr/tf < 1 ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle, VOL(max) 0.4V, VOH(min)
2.7V, Load = 7 pF (stray plus probes).
5 www.national.com
5 Page 
Physical Dimensions
24-Pin TSSOP Package Drawing
Dimensions shown in millimeters
Order Number DS92CK16TMTC
NS Package Number MTC24
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Corporation
Americas
Tel: 1-800-272-9959
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Email: [email protected]
www.national.com
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Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet DS92CK16.PDF ] | |
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