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PDF CY7C019-20AC Data sheet ( Hoja de datos )
| Número de pieza | CY7C019-20AC | |
| Descripción | 64K/128K x 8/9 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C008/009
CY7C018/01964K/128K x 8/9 Dual-Port Static RAM
CY7C008/009
CY7C018/019
64K/128K x 8/9 Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
— Active: ICC = 180 mA (typical)
— Standby: ISB3 = 0.05 mA (typical)
Logic Block Diagram
R/WL
CE0L
CE1L
OEL
CEL
[2]
I/O0L–I/O7/8L
8/9
I/O
Control
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
I/O
Control
CER
R/WR
CE0R
CE1R
OER
8/9 [2]
I/O0R–I/O7/8R
[3]
A0L–A15/16L
16/17
Address
Decode
True Dual-Ported
RAM Array
[3]
A0L–A15/16L
CEL
OEL
R/WL
SEML [4]
BUSYL
INTL
16/17
Notes:
1. See page 6 for Load Conditions.
2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
3. A0–A15 for 64K devices; A0–A16 for 128K.
4. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
Address
Decode
16/17
16/17
[3]
A0R–A15/16R
[3]
A0R–A15/16R
CER
OER
R/WR
SEMR
[4]
BUSYR
INTR
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06041 Rev. *C
Revised June 22, 2004
1 page  
CY7C008/009
CY7C018/019
Electrical Characteristics Over the Operating Range
Parame-
ter
Description
-12[1]
Min. Typ. Max.
VOH Output HIGH Voltage
(VCC=Min., IOH= –4.0 mA)
2.4
VOL Output LOW Voltage
(VCC=Min., IOH= +4.0 mA)
0.4
VIH Input HIGH Voltage
2.2
VIL Input LOW Voltage
0.8
IOZ Output Leakage Current
–10 10
ICC Operating Current
Com’l
(VCC = Max., IOUT=0 mA)
.
Outputs Disabled
Ind.[9]
195 325
ISB1 Standby Current
Com’l
(Both Ports TTL Level)
.
CEL & CER ≥ VIH, f = fMAX Ind.[9]
55 75
ISB2 Standby Current
Com’l
(One Port TTL Level)
.
CEL | CER ≥ VIH, f = fMAX
Ind.[9]
125 205
ISB3 Standby Current
Com’l
(Both Ports CMOS Level)
.
CEL & CER ≥ VCC – 0.2V, f =
0
Ind.[9]
0.05 0.5
ISB4 Standby Current (One Port Com’l
CMOS Level)
.
CEL | CER ≥ VIH, f = fMAX[10] Ind.[9]
115 185
CY7C008/009
CY7C018/019
-15
Min. Typ. Max.
2.4
0.4
2.2
0.8
–10 10
190 280
50 70
120 180
0.05 0.5
110 160
Min.
2.4
2.2
–10
-20
Typ.
180
305
45
60
110
125
0.05
0.05
100
115
Max. Unit
V
0.4 V
V
0.8 V
10 µA
265 mA
290 mA
65 mA
80 mA
160 mA
175 mA
0.5 mA
0.5 mA
140 mA
155 mA
.
Capacitance[11]
Parameter
Description
Test Conditions
Max.
Unit
CIN
COUT
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
10 pF
10 pF
Note:
10. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3
Document #: 38-06041 Rev. *C
Page 5 of 19
5 Page 
CY7C008/009
CY7C018/019
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[35]
A 0–A 2
SEM
VALID ADRESS
tAW
tSCE
tHA
tSAA
VALID ADRESS
tSOP
tACE
tOHA
I/O0
R/W
OE
tSD
DATAIN VALID
tSA
tPWE
tHD
DATAOUT VALID
WRITE CYCLE
tSWRD
tSOP
tDOE
READ CYCLE
Timing Diagram of Semaphore Contention[36, 37, 38]
A0L –A2L
MATCH
R/WL
SEM L
A 0R–A2R
R/WR
SEM R
tSPS
MATCH
Notes:
35. CE = HIGH for the duration of the above timing (both write and read cycle).
36. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
37. Semaphores are reset (available to both ports) at cycle start.
38. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 38-06041 Rev. *C
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY7C019-20AC.PDF ] | |
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