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PDF LTC4257-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC4257-1 | |
| Descripción | Power over Ethernet Interface Controller with Dual Current Limit | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC4257-1
IEEE 802.3af PD
Power over Ethernet Interface
Controller with Dual Current Limit
FEATURES
s Complete Power Interface Port for IEEE 802®.3af
Powered Devices (PDs)
s Onboard 100V, 400mA Power MOSFET
s Precision Dual Level Current Limit
s Onboard 25k Signature Resistor with Disable
s Programmable Classification Current (Class 0-4)
s Undervoltage Lockout
s Thermal Overload Protection
s Power Good Signal
s Available in 8-Pin SO and Low Profile (3mm × 3mm)
DFN Packages
U
APPLICATIO S
s IP Phone Power Management
s Wireless Access Points
s Telecom Power Control
DESCRIPTIO
The LTC®4257-1 provides complete signature and power
interface functions for a device operating in an IEEE
802.3af Power over Ethernet (PoE) system. The LTC4257-1
simplifies Powered Device (PD) design by incorporating
the 25k signature resistor, classification current source,
input current limit, undervoltage lockout, thermal over-
load protection, signature disable and power good signal-
ling, all in a single 8-pin package. The LTC4257-1 includes
a precision, dual level current limit circuit. This allows it to
charge large load capacitors and interface with legacy
Power over Ethernet systems while maintaining compat-
ibility with the current IEEE 802.3af specification. By
incorporating a high voltage power MOSFET onboard, the
LTC4257-1 provides the system designer with reduced
cost while also saving board space.
The LTC4257-1 can interface directly with a variety of Lin-
ear Technology DC/DC converter products to provide a cost
effective power solution for IP phones, wireless access
points and other PDs. Linear Technology also provides
network power controllers for Power Sourcing Equipment
(PSE) applications.
The LTC4257-1 is available in the 8-pin SO and low profile
(3mm × 3mm) DFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
802 is a registered trademark of Institute of Electrical and Electronics Engineers, Inc.
TYPICAL APPLICATIO
Powered Device (PD)
–48V FROM
POWER SOURCING
EQUIPMENT
(PSE)
~+
DF01SA
~–
0.1µF
SMAJ58A
LTC4257-1
GND
RCLASS SIGDISA
RCLASS
PWRGD
VIN VOUT
+
5µF
MIN
100k
VIN
SWITCHING
POWER SUPPLY
SHDN
RTN
+
3.3V
TO LOGIC
–
42571 TA01
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1
1 page  
LTC4257-1
PI FU CTIO S
NC (Pin 1): No Internal Connection.
RCLASS (Pin 2): Class Select Input. Used to set the current
value the LTC4257-1 maintains during classification. Con-
nect a resistor between RCLASS and VIN (see Table 2).
NC (Pin 3): No Internal Connection.
VIN (Pin 4): Power Input. Tie to system – 48V through the
input diode bridge.
VOUT (Pin 5): Power Output. Supplies – 48V to the PD load
through an internal power MOSFET that limits input cur-
rent. VOUT is high impedance until the input voltage rises
above the turn-on UVLO threshold. The output is then
current limited. See Applications Information.
PWRGD (Pin 6): Power Good Output, Open-Drain. Signals
to the PD load that the LTC4257-1 MOSFET is on and that
the PD’s DC/DC converter can start operation. Low imped-
ance indicates power is good. PWRGD is high impedance
during detection, classification and in the event of a
thermal overload. PWRGD is referenced to VIN.
SIGDISA (Pin 7): Signature Disable Input. Allows the PD
to command the LTC4257-1 to present an invalid signa-
ture resistance and to remain inactive. Connecting SIGDISA
to GND lowers the signature resistance to an invalid value.
If left floating, SIGDISA is internally pulled to VIN. If
unused, tie SIGDISA to VIN.
GND (Pin 8): Ground. Tied to system ground and power
return through the input diode bridge.
BLOCK DIAGRA
NC 1
RCLASS 2
CLASSIFICATION
CURRENT LOAD
1.237V
+
– EN
8 GND
25k SIGNATURE
RESISTOR
9k
SIGNATURE DISABLE
16k 7 SIGDISA
NC 3
CONTROL
CIRCUITS
POWER GOOD
6 PWRGD
375mA
140mA
VIN 4
0.3Ω
INPUT
CURRENT
LIMIT
+ EN
–
5 VOUT
BOLD LINE INDICATES HIGH CURRENT PATH
42571 BD
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5 Page 
LTC4257-1
APPLICATIO S I FOR ATIO
accomplished by a dual level current limit. At turn on
before C1 is charged, the LTC4257-1 current limit is set to
the low level. After C1 is charged up and the VOUT – VIN
voltage difference is below the power good threshold, the
LTC4257-1 switches to the high level current limit. The
dual level current limit allows legacy PSEs with limited
current sourcing capability to power up the PD while also
allowing the PD to draw full power from an IEEE 802.3af
PSE.
The dual level current limit also allows use of arbitrarily
large load capacitors. The IEEE 802.3af specification man-
dates that at turn on the PD not exceed the inrush current
limit for more than 50ms. The LTC4257-1 is not restricted
by the 50ms time limit because the load capacitor is
charged with a current below the IEEE inrush current limit
specification. Therefore, it is possible to use larger load
capacitors with the LTC4257-1.
As the LTC4257-1 switches from the low to the high level
current limit, a momenatry increase in current can be
observed. This current spike is a result of the LTC4257-1
charging the last 1.5V at the high level current limit. When
charging a 10µF capacitor, the current spike is typically
100µs wide and 125% of the nominal low level current
limit.
The LTC4257-1 stays in the high level current limit mode
until the input voltage drops below the UVLO turn-off
threshold. This dual level current limit provides the sys-
tem designer with the flexibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
During the current limited turn on, a large amount of power
is dissipated in the power MOSFET. The LTC4257-1 is
designed to accept this thermal load and is thermally
protected to avoid damage to the onboard power MOSFET.
Note that in order to adhere to the IEEE 802.3af standard,
it is necessary for the PD designer to ensure the PD steady-
state power consumption falls within the limits shown in
Table 2.
Power Good
The LTC4257-1 includes a power good circuit (Figure␣ 7)
that is used to indicate to the PD circuitry that load
capacitor C1 is fully charged and that the PD can start
DC/DC converter operation. The power good circuit moni-
tors the voltage across the internal power MOSFET and
PWRGD is asserted when the voltage drops below 1.5V.
The power good circuit includes a large amount of hyster-
esis to allow the LTC4257-1 to operate near the current
limit point without inadvertently disabling PWRGD. The
MOSFET voltage must increase to 3V before PWRGD is
disabled.
LTC4257-1
TO
PSE
4 VIN
THERMAL SHUTDOWN
UVLO
–
PWRGD 6
+
+– 1.125V
R9
100k
C1 +
5µF
MIN
SHDN
PD
LOAD
300k
300k
VOUT 5
42571 F07
Figure 7. LTC4257-1 Power Good
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| PDF Descargar | [ Datasheet LTC4257-1.PDF ] | |
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