PDF CY2305 Data sheet ( Hoja de datos )

Número de pieza	CY2305
Descripción	CY2305 and CY2309 as PCI and SDRAM Buffers
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY2305 and CY2309 as PCI and SDRAM Buffers Introduction to Cypress Zero Delay Buffers What is a Zero Delay Buffer? A zero delay buffer is a device that can fan out 1 clock signal into multiple clock signals with zero delay and very low skew between the outputs. This device is well suited as a buffer for PCI or SDRAM due to its zero input to output delay and very low output to output skew. A simplified diagram of the CY2308 zero delay buffer is shown in Figure 1. The CY2308 is built using a PLL that uses a ref- erence input and a feedback input. The feedback loop is closed by driving the feedback input (FBK) from one of the outputs. The phase detector in the PLL adjusts the output frequency of the VCO so that the two inputs have no phase difference. Since an output is one of the inputs to the PLL, zero phase difference is maintained from REF to the output driving FBK. Now if all outputs are uniformly loaded, zero phase difference will be maintained from REF to all outputs. This is a simple zero delay buffer. Introducing additional de- vices (e.g., dividers) between the output and FBK can give rise to some innovative applications for the PLL, and for fur- ther information on these refer to the Cypress Application Note “CY2308 Zero Delay Buffer”. Since many buffering ap- plications require only a simple closure of the feedback loop, Cypress has designed zero delay buffers with Internal Feed- back Loops: the CY2305 and CY2309. What are the CY2305 and CY2309? Cypress has designed zero delay buffers especially suited for use with PCI or SDRAM buffering. The CY2305 and CY2309 have been designed with the feedback path integrated for simpler system design. A simplified block diagram of the CY2309 zero delay buffer is shown Figure 2. This zero delay buffer uses a input/output pad on CLKOUT so that the feed- back signal can be sensed directly from the output itself. Drive Capability The CY2305 and CY2309 have high drive outputs designed to meet the JEDEC SDRAM specifications of 30 pF capaci- tance on each DIMM clock input. Since the typical CMOS input is 7 pF and the CY2305/09 are designed to drive up to 30 pF; this means that up to 4 CMOS inputs can be driven from a single output of a CY2305/09. However the output loading on the CY2305/09 must be equal on all outputs to maintain zero delay from the input. Power Down The CY2305 and CY2309 have a unique power-down mode: if the input reference is stopped, the part automatically enters a shutdown state, shutting down the PLL and three-stating the outputs. When the part is in shutdown mode it draws less than 50 µA, and can come out of shutdown mode with the PLL locked in less than 1 ms. This power down mode can also be entered by three-stating the input reference driver and allow- ing the internal pull-down to pull the input LOW (the input does not have to go LOW, it only has to stop). 5 Volt to 3.3 Volt Level Shifting The CY2305 and CY2309 can act as a 5-volt to 3.3-volt level shifter. The reference input pad is 5-volt signal-compatible. Since many system components still operate at 5 volts, this feature provides the capability to generate multiple 3.3-volt clocks from a single 5-volt reference clock. This 5-volt sig- nal-compatibility is only available on the reference pad; the other input pads on the CY2309 are not 5-volt compatible. REF Phase Loop Detector Filter VCO PLL MUX S2 Select Input S1 Decoding FBK CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Figure 1. Simplified Block Diagram of CY2308 REF Phase Loop Detector Filter VCO PLL MUX S2 Select Input S1 Decoding CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Figure 2. Simplified Block Diagram of CY2309 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 25, 1997 – Revised July 29, 1997 1 page CY2305 and CY2309 as PCI and SDRAM Buffers Applications 5 and 9 PCI Device/Slot Zero Delay Buffer Solution The CY2305 and CY2309 are an excellent clocking solution for a system that requires more PCI clocks than the currently popular clock chips provide. The CY2305 comes in a tiny 150-mil 8-pin SOIC package and the CY2309 comes in a small 150-mil 16-pin SOIC package. The CY2305 and CY2309 are priced very aggressively for the high volume PC market. There are two solutions for implementing a PCI zero delay buffer with the Cypress zero delay buffers: a 5 de- vice/slot and a 9 device/slot buffer. The 5 Device/Slot Solution: • PCI/Slot 1 (CLKOUT) must always be loaded. • If PCI Slots represent different loads, they will have earlier or later clocks (See Lead or Lag Adjustments section of “Special Features of Cypress Zero Delay Buffers”. PCICLK REF CLKOUT CY2305 Zero Delay Buffer CLK1 CLK2 CLK3 CLK4 PCI Device 1 4 PCI Devices/Slots The 9 Device/Slot Solution: • PCI/Slot 1 (CLKOUT) must always be loaded. • Select lines can be used to shut down output banks, see CY2309 data sheet. PCICLK Vdd REF CLKOUT CLKA1 CLKA2 CY2309 CLKA3 CLKA4 Zero Delay Buffer S1 S2 CLKB1 CLKB2 CLKB3 CLKB4 PCI Device 1 4 PCI Devices/Slots 4 PCI Devices/Slots 1 SDRAM DIMM Zero Delay Buffer Solution The CY2305 is an excellent clocking solution for a system using 1 SDRAM DIMM. The CY2305 comes in a very small 150-mil 8-pin SOIC package and is priced very aggressively for the high volume PC market. There are two solutions for implementing 1 SDRAM DIMM support with the CY2305: the first is the adjustable delay solution, and the second is the self adjusting delay solution. The Adjustable Delay Solution: • Cload must be equal to SDRAM module loading for zero delay. • To make the SDRAM inputs lead or lag the reference input see the Lead or Lag Adjustments section of “Special Fea- tures of the Cypress Zero Delay Buffers”. CPUCLK REF CLKOUT CY2305 Zero Delay Buffer CLK1 CLK2 CLK3 CLK4 Cload SDRAM Module The Self Adjusting Solution: • This solution will automatically compensate for different SDRAM input loads. • CLKOUT must drive CK0 on the SDRAM module so that CLKOUT is always fully loaded (pin 42 on the SDRAM module). CPUCLK REF CLKOUT CY2305 Zero Delay Buffer CLK1 CLK2 CLK3 CLK4 SDRAM Module 5 5 Page

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