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PDF CY2071AFI Data sheet ( Hoja de datos )

Número de pieza CY2071AFI
Descripción Single-PLL General-Purpose EPROM Programmable Clock Generator
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CY2071A
Single-PLL General-Purpose
EPROM Programmable Clock Generator
Features
Benefits
Single phase-locked loop architecture
Generates a custom frequency from an external source
EPROM programmability
Easy customization and fast turnaround
Factory-programmable (CY2071A, CY2071AI) or field- Programming support available for all opportunities
programmable (CY2071AF, CY2071AFI) device options
Up to three configurable outputs
Generates three related frequencies from a single device
Low-skew, low-jitter, high-accuracy outputs
Meets critical industry standard timing requirements
Internal loop filter
Alleviates the need for external components
Power management (OE)
Supports low-power applications
Frequency select options
3 outputs with 2 user selectable frequencies
Configurable 5V or 3.3V operation
Supports industry standard design platforms
8-pin 150-mil SOIC package
Industry-standard packaging saves on board space
i
Selector Guide
Part Number
CY2071A
CY2071AI
CY2071AF
CY2071AFI
Outputs
Input Frequency Range
3 10 MHz25 MHz (external crystal)
1 MHz30 MHz (reference clock)
3 10 MHz25 MHz (external crystal)
1 MHz30 MHz (reference clock)
3 10 MHz25 MHz (external crystal)
1 MHz30 MHz (reference clock)
3 10 MHz25 MHz (external crystal)
1 MHz30 MHz (reference clock)
Output Frequency Range
500 kHz130 MHz (5V)
500 kHz100 MHz (3.3V)
500 kHz100 MHz (5V)
500 kHz80 MHz (3.3V)
500 kHz100 MHz (5V)
500 kHz80 MHz (3.3V)
500 kHz90 MHz (5V)
500 kHz66.6 MHz (3.3V)
Specifics
Factory Programmable
Commercial Temperature
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
Logic Block Diagram for CY2071A
XTALIN
XTALOUT
REFERENCE
OSCILLATOR
PLL
Block
EPROM-
Configurable
Multiplexer
and Divide
Logic
CLKA
CLKB
CLKC
OE / FS
Pin Configuration
CLKA
GND
XTALIN
XTALOUT
8-pin SOIC
Top View
18
27
36
45
OE/FS
VDD
CLKC
CLKB
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07139 Rev. *A
Revised December 14, 2002

1 page




CY2071AFI pdf
CY2071A
Switching Characteristics, Commercial 3.3V[8]
Parameter
Name
Description
t1
Output Period
Clock output range
CY2071AS
3.3V operation
15-pF load
CY2071AF
t1A Clock Jitter
Peak-to-peak period jitter (t1 max. t1 min.),
% of clock period, fOUT 16 MHz
t1B Clock Jitter
Peak-to-peak period jitter
(16 MHz fOUT 50 MHz)
t1C
Clock Jitter[9]
Peak-to-peak period jitter (fOUT > 50 MHz)
Output Duty Cycle
Duty cycle[10, 11] for outputs, (t2 ÷ t1)
fOUT 60 MHz
Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
t3
Rise Time[9]
Output clock rise time
t4
Fall Time[9]
Output clock fall time
t5 Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
Min.
10
[100 MHz]
12.50
[80 MHz]
45%
40%
Typ.
0.8
350
250
50%
50%
1.5
1.5
Max.
2000
[500 kHz]
2000
[500 kHz]
1
Unit
ns
ns
%
500 ps
350
55%
ps
60%
2.5 ns
2.5 ns
0.5 ns
Switching Characteristics, Industrial 5.0V[8]
Parameter
Name
Description
t1
Output Period
Clock output range
CY2071AI
5.0V operation
25-pF load
CY2071AFI
t1A Clock Jitter
Peak-to-peak period jitter (t1 max. t1 min.),
% of clock period, fOUT 16 MHz
t1B Clock Jitter
Peak-to-peak period jitter
(16 MHz fOUT 50 MHz)
t1C
Clock Jitter[9]
Peak-to-peak period jitter (fOUT > 50 MHz)
Min.
10
[100 MHz]
11.1
[90 MHz]
Output Duty Cycle
Duty cycle[10, 11] for outputs, (t2 ÷ t1)
fOUT 60 MHz
Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
t3
Rise time[9]
Output clock rise time
t4 Fall time[9] Output clock fall time
45%
40%
t5 Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
Typ.
0.8
350
250
50%
50%
1.5
1.5
Max.
2000
[500 kHz]
2000
[500 kHz]
1
Unit
ns
ns
%
500 ps
350 ps
55%
60%
2.5 ns
2.5 ns
0.5 ns
Document #: 38-07139 Rev. *A
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