PDF AS7C34098-12 Data sheet ( Hoja de datos )

Número de pieza	AS7C34098-12
Descripción	5V/3.3V 256K 16 CMOS SRAM
Fabricantes	ETC
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No Preview Available ! June 2000 AS7C4098 AS7C34098 ® 5V/3.3V 256K × 16 CMOS SRAM Features • AS7C4098 (5V version) • AS7C34098 (3.3V version) • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 5/6/7/9 ns output enable access time • Low power consumption: ACTIVE - 1375 mW (AS7C4098)/max @ 12 ns - 468 mW (AS7C34098)/max @ 12 ns • Low power consumption: STANDBY - 110 mW (AS7C4098)/max CMOS - 72 mW (AS7C34098)/max CMOS • Individual byte read/write controls • 2.0V data retention • Easy memory expansion with CE, OE inputs • TTL- and CMOS-compatible, three-state I/O • 44-pin JEDEC standard packages - 400-mil SOJ - 400-mil TSOP II • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O I/O9–I/O16 buffer WE 1024 × 256 × 16 Array (4,194,304) Control circuit Column decoder VCC GND UB OE LB CE Selection guide Maximum address access time Maximum output enable access time Maximum operating current AS7C4098 AS7C34098 Maximum CMOS standby current AS7C4098 AS7C34098 Shaded areas indicate preliminary information. AS7C34098 –10 10 5 – 160 – 20 Pin arrangement 44-pin SOJ, TSOP II (400 mil) A0 A1 A2 A3 A4 CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VI/COC12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 AS7C4098 AS7C34098 –12 12 6 250 130 20 20 AS7C4098 AS7C34098 –15 15 7 220 110 20 20 AS7C4098 AS7C34098 –20 20 9 180 100 20 20 Unit ns ns mA mA mA mA 7/21/00 ALLIANCE SEMICONDUCTOR 1 Copyright ©2000 Alliance Semiconductor. All rights reserved. 1 page AS7C4098 AS7C34098 ® Write cycle (over the operating range) –10 –12 –15 –20 Parameter Symbol Min Max Min Max Min Max Min Max Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width (OE = High) Write pulse width (OE = Low) tWC 10 – 12 – 15 – 20 – tCW 7 – 8 – 10 – 12 – tAW 7 – 8 – 10 – 12 – tAS 0 – 0 – 0 – 0 – tWP1 7 – 8 – 10 – 12 – tWP2 10 – 12 – 15 – 20 – Address hold from end of write tAH 0 – 0 – 0 – 0 – Data valid to write end tDW 5 6 7 – 9 – Data hold time tDH 0 – 0 – 0 – 0 – Write enable to output in High-Z tWZ 0 5 0 6 0 7 0 9 Output active from write end tOW 3 – 3 – 3 – 3 – Byte enable Low to write end tBW 7 – 8 – 10 – 12 – Shaded areas indicate prelimin ary information. Write waveform 1(WE controlled) Address CE LB, UB WE tAS tWC tCW tBW tAW DataIN DataOUT Data undefined tWZ tAH tWP tDW tDH Data valid tOW High Z Write waveform 2 (CE controlled) Address CE tAS LB, UB WE DataIN DataOUT tCLZ High Z tWC tCW tAW tBW tAH tWP tWZ Data undefined tDW tDH Data valid tOW High Z Unit Note ns ns ns ns ns ns ns ns ns 4, 5 ns 4, 5 ns 4, 5 ns 4, 5 7/21/00 ALLIANCE SEMICONDUCTOR 5 5 Page

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